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1 ; RUN: llc -O0 -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
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77
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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2
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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3 define void @t0(i32 %a) nounwind {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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4 entry:
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
5 ; CHECK: t0
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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6 ; CHECK: str {{w[0-9]+}}, [sp, #12]
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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7 ; CHECK-NEXT: ldr [[REGISTER:w[0-9]+]], [sp, #12]
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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8 ; CHECK-NEXT: str [[REGISTER]], [sp, #12]
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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9 ; CHECK: ret
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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10 %a.addr = alloca i32, align 4
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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11 store i32 %a, i32* %a.addr
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95
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12 %tmp = load i32, i32* %a.addr
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77
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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13 store i32 %tmp, i32* %a.addr
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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14 ret void
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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15 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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16
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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17 define void @t1(i64 %a) nounwind {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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18 ; CHECK: t1
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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19 ; CHECK: str {{x[0-9]+}}, [sp, #8]
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
20 ; CHECK-NEXT: ldr [[REGISTER:x[0-9]+]], [sp, #8]
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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21 ; CHECK-NEXT: str [[REGISTER]], [sp, #8]
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
22 ; CHECK: ret
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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23 %a.addr = alloca i64, align 4
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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24 store i64 %a, i64* %a.addr
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95
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25 %tmp = load i64, i64* %a.addr
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77
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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26 store i64 %tmp, i64* %a.addr
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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27 ret void
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
28 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
29
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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30 define zeroext i1 @i1(i1 %a) nounwind {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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31 entry:
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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32 ; CHECK: @i1
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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33 ; CHECK: and w0, w0, #0x1
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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34 ; CHECK: strb w0, [sp, #15]
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
35 ; CHECK: ldrb w0, [sp, #15]
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
36 ; CHECK: and w0, w0, #0x1
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
37 ; CHECK: and w0, w0, #0x1
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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38 ; CHECK: add sp, sp, #16
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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39 ; CHECK: ret
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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40 %a.addr = alloca i1, align 1
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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41 store i1 %a, i1* %a.addr, align 1
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95
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42 %0 = load i1, i1* %a.addr, align 1
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77
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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43 ret i1 %0
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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44 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
45
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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46 define i32 @t2(i32 *%ptr) nounwind {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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47 entry:
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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48 ; CHECK-LABEL: t2:
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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49 ; CHECK: ldur w0, [x0, #-4]
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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50 ; CHECK: ret
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95
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51 %0 = getelementptr i32, i32 *%ptr, i32 -1
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52 %1 = load i32, i32* %0, align 4
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77
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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53 ret i32 %1
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
54 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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55
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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56 define i32 @t3(i32 *%ptr) nounwind {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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57 entry:
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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58 ; CHECK-LABEL: t3:
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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59 ; CHECK: ldur w0, [x0, #-256]
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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60 ; CHECK: ret
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95
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61 %0 = getelementptr i32, i32 *%ptr, i32 -64
|
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62 %1 = load i32, i32* %0, align 4
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77
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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63 ret i32 %1
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
64 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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65
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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66 define void @t4(i32 *%ptr) nounwind {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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67 entry:
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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68 ; CHECK-LABEL: t4:
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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69 ; CHECK: stur wzr, [x0, #-4]
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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70 ; CHECK: ret
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95
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71 %0 = getelementptr i32, i32 *%ptr, i32 -1
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77
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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72 store i32 0, i32* %0, align 4
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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73 ret void
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
74 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
75
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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76 define void @t5(i32 *%ptr) nounwind {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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77 entry:
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
78 ; CHECK-LABEL: t5:
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
79 ; CHECK: stur wzr, [x0, #-256]
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
80 ; CHECK: ret
|
95
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81 %0 = getelementptr i32, i32 *%ptr, i32 -64
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77
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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82 store i32 0, i32* %0, align 4
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
83 ret void
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
84 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
85
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
86 define void @t6() nounwind {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
87 ; CHECK: t6
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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88 ; CHECK: brk #0x1
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
89 tail call void @llvm.trap()
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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90 ret void
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
91 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
92
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
93 declare void @llvm.trap() nounwind
|
95
|
94
|
|
95 define void @ands(i32* %addr) {
|
|
96 ; CHECK-LABEL: ands:
|
|
97 ; CHECK: tst [[COND:w[0-9]+]], #0x1
|
|
98 ; CHECK-NEXT: csel [[COND]],
|
|
99 entry:
|
|
100 %cond91 = select i1 undef, i32 1, i32 2
|
|
101 store i32 %cond91, i32* %addr, align 4
|
|
102 ret void
|
|
103 }
|
|
104
|
|
105 define i64 @mul_umul(i64 %arg) {
|
|
106 ; CHECK-LABEL: mul_umul:
|
|
107 ; CHECK: mul x{{[0-9]+}}, [[ARG1:x[0-9]+]], [[ARG2:x[0-9]+]]
|
|
108 ; CHECK-NEXT: umulh x{{[0-9]+}}, [[ARG1]], [[ARG2]]
|
|
109 entry:
|
|
110 %sub.ptr.div = sdiv exact i64 %arg, 8
|
|
111 %tmp = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %sub.ptr.div, i64 8)
|
|
112 %tmp1 = extractvalue { i64, i1 } %tmp, 0
|
|
113 ret i64 %tmp1
|
|
114 }
|
|
115
|
|
116 declare { i64, i1 } @llvm.umul.with.overflow.i64(i64, i64)
|
|
117
|
|
118 define void @logicalReg() {
|
|
119 ; Make sure we generate a logical reg = reg, reg instruction without any
|
|
120 ; machine verifier errors.
|
|
121 ; CHECK-LABEL: logicalReg:
|
|
122 ; CHECK: orr w{{[0-9]+}}, w{{[0-9]+}}, w{{[0-9]+}}
|
|
123 ; CHECK: ret
|
|
124 entry:
|
|
125 br i1 undef, label %cond.end, label %cond.false
|
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126
|
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127 cond.false:
|
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128 %cond = select i1 undef, i1 true, i1 false
|
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129 br label %cond.end
|
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130
|
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131 cond.end:
|
|
132 %cond13 = phi i1 [ %cond, %cond.false ], [ true, %entry ]
|
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133 ret void
|
|
134 }
|
|
135
|