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83
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1 ; RUN: llc -mtriple=aarch64-apple-darwin -verify-machineinstrs < %s | FileCheck %s
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95
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2 ; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s
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83
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3
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4 ; First test the different supported value types for select.
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5 define zeroext i1 @select_i1(i1 zeroext %c, i1 zeroext %a, i1 zeroext %b) {
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6 ; CHECK-LABEL: select_i1
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7 ; CHECK: {{cmp w0, #0|tst w0, #0x1}}
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8 ; CHECK-NEXT: csel {{w[0-9]+}}, w1, w2, ne
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9 %1 = select i1 %c, i1 %a, i1 %b
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10 ret i1 %1
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11 }
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12
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13 define zeroext i8 @select_i8(i1 zeroext %c, i8 zeroext %a, i8 zeroext %b) {
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14 ; CHECK-LABEL: select_i8
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15 ; CHECK: {{cmp w0, #0|tst w0, #0x1}}
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16 ; CHECK-NEXT: csel {{w[0-9]+}}, w1, w2, ne
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17 %1 = select i1 %c, i8 %a, i8 %b
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18 ret i8 %1
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19 }
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20
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21 define zeroext i16 @select_i16(i1 zeroext %c, i16 zeroext %a, i16 zeroext %b) {
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22 ; CHECK-LABEL: select_i16
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23 ; CHECK: {{cmp w0, #0|tst w0, #0x1}}
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24 ; CHECK-NEXT: csel {{w[0-9]+}}, w1, w2, ne
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25 %1 = select i1 %c, i16 %a, i16 %b
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26 ret i16 %1
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27 }
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28
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29 define i32 @select_i32(i1 zeroext %c, i32 %a, i32 %b) {
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30 ; CHECK-LABEL: select_i32
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31 ; CHECK: {{cmp w0, #0|tst w0, #0x1}}
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32 ; CHECK-NEXT: csel {{w[0-9]+}}, w1, w2, ne
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33 %1 = select i1 %c, i32 %a, i32 %b
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34 ret i32 %1
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35 }
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36
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37 define i64 @select_i64(i1 zeroext %c, i64 %a, i64 %b) {
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38 ; CHECK-LABEL: select_i64
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39 ; CHECK: {{cmp w0, #0|tst w0, #0x1}}
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40 ; CHECK-NEXT: csel {{x[0-9]+}}, x1, x2, ne
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41 %1 = select i1 %c, i64 %a, i64 %b
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42 ret i64 %1
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43 }
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44
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45 define float @select_f32(i1 zeroext %c, float %a, float %b) {
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46 ; CHECK-LABEL: select_f32
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47 ; CHECK: {{cmp w0, #0|tst w0, #0x1}}
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48 ; CHECK-NEXT: fcsel {{s[0-9]+}}, s0, s1, ne
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49 %1 = select i1 %c, float %a, float %b
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50 ret float %1
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51 }
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52
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53 define double @select_f64(i1 zeroext %c, double %a, double %b) {
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54 ; CHECK-LABEL: select_f64
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55 ; CHECK: {{cmp w0, #0|tst w0, #0x1}}
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56 ; CHECK-NEXT: fcsel {{d[0-9]+}}, d0, d1, ne
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57 %1 = select i1 %c, double %a, double %b
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58 ret double %1
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59 }
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60
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61 ; Now test the folding of all compares.
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62 define float @select_fcmp_false(float %x, float %a, float %b) {
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63 ; CHECK-LABEL: select_fcmp_false
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64 ; CHECK: mov.16b {{v[0-9]+}}, v2
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65 %1 = fcmp ogt float %x, %x
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66 %2 = select i1 %1, float %a, float %b
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67 ret float %2
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68 }
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69
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70 define float @select_fcmp_ogt(float %x, float %y, float %a, float %b) {
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71 ; CHECK-LABEL: select_fcmp_ogt
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72 ; CHECK: fcmp s0, s1
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73 ; CHECK-NEXT: fcsel {{s[0-9]+}}, s2, s3, gt
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74 %1 = fcmp ogt float %x, %y
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75 %2 = select i1 %1, float %a, float %b
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76 ret float %2
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77 }
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78
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79 define float @select_fcmp_oge(float %x, float %y, float %a, float %b) {
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80 ; CHECK-LABEL: select_fcmp_oge
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81 ; CHECK: fcmp s0, s1
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82 ; CHECK-NEXT: fcsel {{s[0-9]+}}, s2, s3, ge
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83 %1 = fcmp oge float %x, %y
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84 %2 = select i1 %1, float %a, float %b
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85 ret float %2
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86 }
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87
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88 define float @select_fcmp_olt(float %x, float %y, float %a, float %b) {
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89 ; CHECK-LABEL: select_fcmp_olt
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90 ; CHECK: fcmp s0, s1
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91 ; CHECK-NEXT: fcsel {{s[0-9]+}}, s2, s3, mi
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92 %1 = fcmp olt float %x, %y
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93 %2 = select i1 %1, float %a, float %b
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94 ret float %2
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95 }
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96
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97 define float @select_fcmp_ole(float %x, float %y, float %a, float %b) {
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98 ; CHECK-LABEL: select_fcmp_ole
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99 ; CHECK: fcmp s0, s1
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100 ; CHECK-NEXT: fcsel {{s[0-9]+}}, s2, s3, ls
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101 %1 = fcmp ole float %x, %y
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102 %2 = select i1 %1, float %a, float %b
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103 ret float %2
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104 }
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105
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106 define float @select_fcmp_one(float %x, float %y, float %a, float %b) {
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107 ; CHECK-LABEL: select_fcmp_one
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108 ; CHECK: fcmp s0, s1
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109 ; CHECK-NEXT: fcsel [[REG:s[0-9]+]], s2, s3, mi
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110 ; CHECK-NEXT: fcsel {{s[0-9]+}}, s2, [[REG]], gt
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111 %1 = fcmp one float %x, %y
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112 %2 = select i1 %1, float %a, float %b
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113 ret float %2
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114 }
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115
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116 define float @select_fcmp_ord(float %x, float %y, float %a, float %b) {
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117 ; CHECK-LABEL: select_fcmp_ord
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118 ; CHECK: fcmp s0, s1
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119 ; CHECK-NEXT: fcsel {{s[0-9]+}}, s2, s3, vc
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120 %1 = fcmp ord float %x, %y
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121 %2 = select i1 %1, float %a, float %b
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122 ret float %2
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123 }
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124
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125 define float @select_fcmp_uno(float %x, float %y, float %a, float %b) {
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126 ; CHECK-LABEL: select_fcmp_uno
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127 ; CHECK: fcmp s0, s1
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128 ; CHECK-NEXT: fcsel {{s[0-9]+}}, s2, s3, vs
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129 %1 = fcmp uno float %x, %y
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130 %2 = select i1 %1, float %a, float %b
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131 ret float %2
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132 }
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133
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134 define float @select_fcmp_ueq(float %x, float %y, float %a, float %b) {
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135 ; CHECK-LABEL: select_fcmp_ueq
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136 ; CHECK: fcmp s0, s1
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137 ; CHECK-NEXT: fcsel [[REG:s[0-9]+]], s2, s3, eq
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138 ; CHECK-NEXT: fcsel {{s[0-9]+}}, s2, [[REG]], vs
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139 %1 = fcmp ueq float %x, %y
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140 %2 = select i1 %1, float %a, float %b
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141 ret float %2
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142 }
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143
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144 define float @select_fcmp_ugt(float %x, float %y, float %a, float %b) {
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145 ; CHECK-LABEL: select_fcmp_ugt
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146 ; CHECK: fcmp s0, s1
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147 ; CHECK-NEXT: fcsel {{s[0-9]+}}, s2, s3, hi
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148 %1 = fcmp ugt float %x, %y
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149 %2 = select i1 %1, float %a, float %b
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150 ret float %2
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151 }
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152
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153 define float @select_fcmp_uge(float %x, float %y, float %a, float %b) {
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154 ; CHECK-LABEL: select_fcmp_uge
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155 ; CHECK: fcmp s0, s1
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156 ; CHECK-NEXT: fcsel {{s[0-9]+}}, s2, s3, pl
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157 %1 = fcmp uge float %x, %y
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158 %2 = select i1 %1, float %a, float %b
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159 ret float %2
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160 }
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161
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162 define float @select_fcmp_ult(float %x, float %y, float %a, float %b) {
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163 ; CHECK-LABEL: select_fcmp_ult
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164 ; CHECK: fcmp s0, s1
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165 ; CHECK-NEXT: fcsel {{s[0-9]+}}, s2, s3, lt
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166 %1 = fcmp ult float %x, %y
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167 %2 = select i1 %1, float %a, float %b
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168 ret float %2
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169 }
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170
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171
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172 define float @select_fcmp_ule(float %x, float %y, float %a, float %b) {
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173 ; CHECK-LABEL: select_fcmp_ule
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174 ; CHECK: fcmp s0, s1
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175 ; CHECK-NEXT: fcsel {{s[0-9]+}}, s2, s3, le
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176 %1 = fcmp ule float %x, %y
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177 %2 = select i1 %1, float %a, float %b
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178 ret float %2
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179 }
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180
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181 define float @select_fcmp_une(float %x, float %y, float %a, float %b) {
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182 ; CHECK-LABEL: select_fcmp_une
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183 ; CHECK: fcmp s0, s1
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184 ; CHECK-NEXT: fcsel {{s[0-9]+}}, s2, s3, ne
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185 %1 = fcmp une float %x, %y
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186 %2 = select i1 %1, float %a, float %b
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187 ret float %2
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188 }
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189
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190 define float @select_fcmp_true(float %x, float %a, float %b) {
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191 ; CHECK-LABEL: select_fcmp_true
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192 ; CHECK: mov.16b {{v[0-9]+}}, v1
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193 %1 = fcmp ueq float %x, %x
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194 %2 = select i1 %1, float %a, float %b
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195 ret float %2
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196 }
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197
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198 define float @select_icmp_eq(i32 %x, i32 %y, float %a, float %b) {
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199 ; CHECK-LABEL: select_icmp_eq
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200 ; CHECK: cmp w0, w1
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201 ; CHECK-NEXT: fcsel {{s[0-9]+}}, s0, s1, eq
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202 %1 = icmp eq i32 %x, %y
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203 %2 = select i1 %1, float %a, float %b
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204 ret float %2
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205 }
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206
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207 define float @select_icmp_ne(i32 %x, i32 %y, float %a, float %b) {
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208 ; CHECK-LABEL: select_icmp_ne
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209 ; CHECK: cmp w0, w1
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210 ; CHECK-NEXT: fcsel {{s[0-9]+}}, s0, s1, ne
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211 %1 = icmp ne i32 %x, %y
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212 %2 = select i1 %1, float %a, float %b
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213 ret float %2
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214 }
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215
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216 define float @select_icmp_ugt(i32 %x, i32 %y, float %a, float %b) {
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217 ; CHECK-LABEL: select_icmp_ugt
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218 ; CHECK: cmp w0, w1
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219 ; CHECK-NEXT: fcsel {{s[0-9]+}}, s0, s1, hi
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220 %1 = icmp ugt i32 %x, %y
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221 %2 = select i1 %1, float %a, float %b
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222 ret float %2
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223 }
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224
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225 define float @select_icmp_uge(i32 %x, i32 %y, float %a, float %b) {
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226 ; CHECK-LABEL: select_icmp_uge
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227 ; CHECK: cmp w0, w1
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228 ; CHECK-NEXT: fcsel {{s[0-9]+}}, s0, s1, hs
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229 %1 = icmp uge i32 %x, %y
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230 %2 = select i1 %1, float %a, float %b
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231 ret float %2
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232 }
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233
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234 define float @select_icmp_ult(i32 %x, i32 %y, float %a, float %b) {
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235 ; CHECK-LABEL: select_icmp_ult
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236 ; CHECK: cmp w0, w1
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237 ; CHECK-NEXT: fcsel {{s[0-9]+}}, s0, s1, lo
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238 %1 = icmp ult i32 %x, %y
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239 %2 = select i1 %1, float %a, float %b
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240 ret float %2
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241 }
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242
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243 define float @select_icmp_ule(i32 %x, i32 %y, float %a, float %b) {
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244 ; CHECK-LABEL: select_icmp_ule
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245 ; CHECK: cmp w0, w1
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246 ; CHECK-NEXT: fcsel {{s[0-9]+}}, s0, s1, ls
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247 %1 = icmp ule i32 %x, %y
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248 %2 = select i1 %1, float %a, float %b
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249 ret float %2
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250 }
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251
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252 define float @select_icmp_sgt(i32 %x, i32 %y, float %a, float %b) {
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253 ; CHECK-LABEL: select_icmp_sgt
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254 ; CHECK: cmp w0, w1
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255 ; CHECK-NEXT: fcsel {{s[0-9]+}}, s0, s1, gt
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256 %1 = icmp sgt i32 %x, %y
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257 %2 = select i1 %1, float %a, float %b
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258 ret float %2
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259 }
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260
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261 define float @select_icmp_sge(i32 %x, i32 %y, float %a, float %b) {
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262 ; CHECK-LABEL: select_icmp_sge
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263 ; CHECK: cmp w0, w1
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264 ; CHECK-NEXT: fcsel {{s[0-9]+}}, s0, s1, ge
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265 %1 = icmp sge i32 %x, %y
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266 %2 = select i1 %1, float %a, float %b
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267 ret float %2
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268 }
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269
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270 define float @select_icmp_slt(i32 %x, i32 %y, float %a, float %b) {
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271 ; CHECK-LABEL: select_icmp_slt
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272 ; CHECK: cmp w0, w1
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273 ; CHECK-NEXT: fcsel {{s[0-9]+}}, s0, s1, lt
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274 %1 = icmp slt i32 %x, %y
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275 %2 = select i1 %1, float %a, float %b
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276 ret float %2
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277 }
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278
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279 define float @select_icmp_sle(i32 %x, i32 %y, float %a, float %b) {
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280 ; CHECK-LABEL: select_icmp_sle
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281 ; CHECK: cmp w0, w1
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282 ; CHECK-NEXT: fcsel {{s[0-9]+}}, s0, s1, le
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283 %1 = icmp sle i32 %x, %y
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284 %2 = select i1 %1, float %a, float %b
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285 ret float %2
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286 }
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287
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288 ; Test peephole optimizations for select.
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289 define zeroext i1 @select_opt1(i1 zeroext %c, i1 zeroext %a) {
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290 ; CHECK-LABEL: select_opt1
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291 ; CHECK: orr {{w[0-9]+}}, w0, w1
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292 %1 = select i1 %c, i1 true, i1 %a
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293 ret i1 %1
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294 }
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295
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296 define zeroext i1 @select_opt2(i1 zeroext %c, i1 zeroext %a) {
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297 ; CHECK-LABEL: select_opt2
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298 ; CHECK: eor [[REG:w[0-9]+]], w0, #0x1
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299 ; CHECK: orr {{w[0-9]+}}, [[REG]], w1
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300 %1 = select i1 %c, i1 %a, i1 true
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301 ret i1 %1
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302 }
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303
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304 define zeroext i1 @select_opt3(i1 zeroext %c, i1 zeroext %a) {
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305 ; CHECK-LABEL: select_opt3
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306 ; CHECK: bic {{w[0-9]+}}, w1, w0
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307 %1 = select i1 %c, i1 false, i1 %a
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308 ret i1 %1
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309 }
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310
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311 define zeroext i1 @select_opt4(i1 zeroext %c, i1 zeroext %a) {
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312 ; CHECK-LABEL: select_opt4
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313 ; CHECK: and {{w[0-9]+}}, w0, w1
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314 %1 = select i1 %c, i1 %a, i1 false
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315 ret i1 %1
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316 }
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