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annotate test/CodeGen/AArch64/machine-copy-prop.ll @ 117:facf19d07cd9

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check EHStack on EmitCall (CbC goto)
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Wed, 24 Aug 2016 20:10:41 +0900
parents afa8332a0e37
children
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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1 ; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=cortex-a57 -verify-machineinstrs < %s | FileCheck %s
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2
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3 ; This file check a bug in MachineCopyPropagation pass. The last COPY will be
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4 ; incorrectly removed if the machine instructions are as follows:
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5 ; %Q5_Q6<def> = COPY %Q2_Q3
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6 ; %D5<def> =
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7 ; %D3<def> =
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8 ; %D3<def> = COPY %D6
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9 ; This is caused by a bug in function SourceNoLongerAvailable(), which fails to
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10 ; remove the relationship of D6 and "%Q5_Q6<def> = COPY %Q2_Q3".
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11
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12 @failed = internal unnamed_addr global i1 false
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13
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14 ; CHECK-LABEL: foo:
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15 ; CHECK: ld2
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16 ; CHECK-NOT: // kill: D{{[0-9]+}}<def> D{{[0-9]+}}<kill>
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17 define void @foo(<2 x i32> %shuffle251, <8 x i8> %vtbl1.i, i8* %t2, <2 x i32> %vrsubhn_v2.i1364) {
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18 entry:
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19 %val0 = alloca [2 x i64], align 8
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20 %val1 = alloca <2 x i64>, align 16
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21 %vmull = tail call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> <i32 -1, i32 -1>, <2 x i32> %shuffle251)
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22 %vgetq_lane = extractelement <2 x i64> %vmull, i32 0
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23 %cmp = icmp eq i64 %vgetq_lane, 1
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24 br i1 %cmp, label %if.end, label %if.then
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25
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26 if.then: ; preds = %entry
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27 store i1 true, i1* @failed, align 1
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28 br label %if.end
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29
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30 if.end: ; preds = %if.then, %entry
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31 tail call void @f2()
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32 %sqdmull = tail call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> <i16 1, i16 0, i16 0, i16 0>, <4 x i16> <i16 2, i16 0, i16 0, i16 0>)
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33 %sqadd = tail call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> zeroinitializer, <4 x i32> %sqdmull)
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34 %shuffle = shufflevector <4 x i32> %sqadd, <4 x i32> undef, <2 x i32> zeroinitializer
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35 %0 = mul <2 x i32> %shuffle, <i32 -1, i32 0>
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36 %sub = add <2 x i32> %0, <i32 1, i32 0>
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37 %sext = sext <2 x i32> %sub to <2 x i64>
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38 %vset_lane603 = shufflevector <2 x i64> %sext, <2 x i64> undef, <1 x i32> zeroinitializer
afa8332a0e37 LLVM 3.8
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39 %t1 = bitcast [2 x i64]* %val0 to i8*
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40 call void @llvm.aarch64.neon.st2lane.v2i64.p0i8(<2 x i64> zeroinitializer, <2 x i64> zeroinitializer, i64 1, i8* %t1)
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41 call void @llvm.aarch64.neon.st2lane.v1i64.p0i8(<1 x i64> <i64 4096>, <1 x i64> <i64 -1>, i64 0, i8* %t2)
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42 %vld2_lane = call { <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld2lane.v1i64.p0i8(<1 x i64> <i64 11>, <1 x i64> <i64 11>, i64 0, i8* %t2)
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43 %vld2_lane.0.extract = extractvalue { <1 x i64>, <1 x i64> } %vld2_lane, 0
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44 %vld2_lane.1.extract = extractvalue { <1 x i64>, <1 x i64> } %vld2_lane, 1
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45 %vld2_lane1 = call { <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld2lane.v1i64.p0i8(<1 x i64> %vld2_lane.0.extract, <1 x i64> %vld2_lane.1.extract, i64 0, i8* %t1)
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46 %vld2_lane1.0.extract = extractvalue { <1 x i64>, <1 x i64> } %vld2_lane1, 0
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47 %vld2_lane1.1.extract = extractvalue { <1 x i64>, <1 x i64> } %vld2_lane1, 1
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48 %t3 = bitcast <2 x i64>* %val1 to i8*
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49 call void @llvm.aarch64.neon.st2.v1i64.p0i8(<1 x i64> %vld2_lane1.0.extract, <1 x i64> %vld2_lane1.1.extract, i8* %t3)
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50 %t4 = load <2 x i64>, <2 x i64>* %val1, align 16
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51 %vsubhn = sub <2 x i64> <i64 11, i64 0>, %t4
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52 %vsubhn1 = lshr <2 x i64> %vsubhn, <i64 32, i64 32>
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53 %vsubhn2 = trunc <2 x i64> %vsubhn1 to <2 x i32>
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54 %neg = xor <2 x i32> %vsubhn2, <i32 -1, i32 -1>
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55 %sqadd1 = call <1 x i64> @llvm.aarch64.neon.usqadd.v1i64(<1 x i64> <i64 -1>, <1 x i64> <i64 1>)
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56 %sqadd2 = call <1 x i64> @llvm.aarch64.neon.usqadd.v1i64(<1 x i64> %vset_lane603, <1 x i64> %sqadd1)
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57 %sqadd3 = call <1 x i64> @llvm.aarch64.neon.usqadd.v1i64(<1 x i64> <i64 1>, <1 x i64> %sqadd2)
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58 %shuffle.i = shufflevector <2 x i32> <i32 undef, i32 0>, <2 x i32> %vrsubhn_v2.i1364, <2 x i32> <i32 1, i32 3>
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59 %cmp.i = icmp uge <2 x i32> %shuffle.i, %neg
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60 %sext.i = sext <2 x i1> %cmp.i to <2 x i32>
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61 %vpadal = call <1 x i64> @llvm.aarch64.neon.uaddlp.v1i64.v2i32(<2 x i32> %sext.i)
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62 %t5 = sub <1 x i64> %vpadal, %sqadd3
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63 %vget_lane1 = extractelement <1 x i64> %t5, i32 0
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64 %cmp2 = icmp eq i64 %vget_lane1, 15
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65 br i1 %cmp2, label %if.end2, label %if.then2
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66
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67 if.then2: ; preds = %if.end
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68 store i1 true, i1* @failed, align 1
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69 br label %if.end2
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70
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71 if.end2: ; preds = %if.then682, %if.end
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72 call void @f2()
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73 %vext = shufflevector <8 x i8> <i8 undef, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <8 x i8> %vtbl1.i, <8 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8>
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74 %t6 = bitcast <8 x i8> %vext to <2 x i32>
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75 call void @f0(<2 x i32> %t6)
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76 ret void
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77 }
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78
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79 declare void @f0(<2 x i32>)
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80
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81 declare <8 x i8> @f1()
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82
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83 declare void @f2()
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84
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85 declare <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16>, <4 x i16>)
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86
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87 declare void @llvm.aarch64.neon.st2lane.v2i64.p0i8(<2 x i64>, <2 x i64>, i64, i8* nocapture)
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88
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89 declare void @llvm.aarch64.neon.st2lane.v1i64.p0i8(<1 x i64>, <1 x i64>, i64, i8* nocapture)
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90
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91 declare { <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld2lane.v1i64.p0i8(<1 x i64>, <1 x i64>, i64, i8*)
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92
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93 declare void @llvm.aarch64.neon.st2.v1i64.p0i8(<1 x i64>, <1 x i64>, i8* nocapture)
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94
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95 declare <1 x i64> @llvm.aarch64.neon.usqadd.v1i64(<1 x i64>, <1 x i64>)
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96
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97 declare <1 x i64> @llvm.aarch64.neon.uaddlp.v1i64.v2i32(<2 x i32>)
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98
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99 declare <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32>, <4 x i32>)
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100
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101 declare <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32>, <2 x i32>)