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annotate test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll @ 117:facf19d07cd9

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author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Wed, 24 Aug 2016 20:10:41 +0900
parents afa8332a0e37
children 1172e4bd9c6f
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afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
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1 ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \
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Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
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2 ; RUN: < %s | FileCheck %s
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3 ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \
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parents:
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4 ; RUN: < %s | FileCheck %s
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parents: 83
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5 ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \
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parents: 77
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6 ; RUN: < %s | FileCheck %s -check-prefix=mips32r2
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parents: 83
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7 ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \
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parents: 77
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8 ; RUN: < %s | FileCheck %s -check-prefix=mips32
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parents:
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9
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10 @f = common global float 0.000000e+00, align 4
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11 @de = common global double 0.000000e+00, align 8
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12
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13 ; Function Attrs: nounwind
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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14 define void @f1() #0 {
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15 entry:
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16 store float 0x3FFA76C8C0000000, float* @f, align 4
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17 ret void
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18 ; CHECK: .ent f1
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19 ; CHECK: lui $[[REG1:[0-9]+]], 16339
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20 ; CHECK: ori $[[REG2:[0-9]+]], $[[REG1]], 46662
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21 ; CHECK: mtc1 $[[REG2]], $f[[REG3:[0-9]+]]
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22 ; CHECK: lw $[[REG4:[0-9]+]], %got(f)(${{[0-9]+}})
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parents:
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23 ; CHECK: swc1 $f[[REG3]], 0($[[REG4]])
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24 ; CHECK: .end f1
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25
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26 }
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27
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28 ; Function Attrs: nounwind
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29 define void @d1() #0 {
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30 entry:
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31 store double 1.234567e+00, double* @de, align 8
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parents: 77
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32 ; mip32r2: .ent d1
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parents: 77
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33 ; mips32r2: lui $[[REG1a:[0-9]+]], 16371
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parents: 77
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34 ; mips32r2: ori $[[REG2a:[0-9]+]], $[[REG1a]], 49353
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parents: 77
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35 ; mips32r2: lui $[[REG1b:[0-9]+]], 21403
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parents: 77
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36 ; mips32r2: ori $[[REG2b:[0-9]+]], $[[REG1b]], 34951
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parents: 77
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37 ; mips32r2: mtc1 $[[REG2b]], $f[[REG3:[0-9]+]]
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parents: 77
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38 ; mips32r2: mthc1 $[[REG2a]], $f[[REG3]]
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parents: 77
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39 ; mips32r2: sdc1 $f[[REG3]], 0(${{[0-9]+}})
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parents: 77
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40 ; mips32r2: .end d1
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Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
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41 ; mips32: .ent d1
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parents: 77
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42 ; mips32: lui $[[REG1a:[0-9]+]], 16371
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Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
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43 ; mips32: ori $[[REG2a:[0-9]+]], $[[REG1a]], 49353
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Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
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44 ; mips32: lui $[[REG1b:[0-9]+]], 21403
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parents: 77
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45 ; mips32: ori $[[REG2b:[0-9]+]], $[[REG1b]], 34951
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parents: 77
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46 ; mips32: mtc1 $[[REG2b]], $f[[REG3:[0-9]+]]
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parents: 77
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47 ; mips32: mtc1 $[[REG2a]], $f{{[0-9]+}}
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parents: 77
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48 ; mips32: sdc1 $f[[REG3]], 0(${{[0-9]+}})
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parents: 77
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49 ; mips32: .end d1
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parents: 77
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50
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51 ret void
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52 }
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53
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54 attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }