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83
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1 ; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
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2 ; RUN: -check-prefix=ALL -check-prefix=M2 -check-prefix=M2-M3
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3 ; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
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4 ; RUN: -check-prefix=ALL -check-prefix=CMOV \
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5 ; RUN: -check-prefix=CMOV-32 -check-prefix=CMOV-32R1
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6 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
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7 ; RUN: -check-prefix=ALL -check-prefix=CMOV \
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95
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8 ; RUN: -check-prefix=CMOV-32 -check-prefix=CMOV-32R2-R5
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9 ; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
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10 ; RUN: -check-prefix=ALL -check-prefix=CMOV \
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11 ; RUN: -check-prefix=CMOV-32 -check-prefix=CMOV-32R2-R5
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12 ; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
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13 ; RUN: -check-prefix=ALL -check-prefix=CMOV \
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14 ; RUN: -check-prefix=CMOV-32 -check-prefix=CMOV-32R2-R5
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83
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15 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
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16 ; RUN: -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-32
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17 ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
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18 ; RUN: -check-prefix=ALL -check-prefix=M3 -check-prefix=M2-M3
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19 ; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
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20 ; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
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21 ; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
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22 ; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
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23 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
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24 ; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
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95
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25 ; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
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26 ; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
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27 ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
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28 ; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
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83
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29 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
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30 ; RUN: -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-64
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31
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32 define signext i1 @tst_select_i1_i1(i1 signext %s,
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33 i1 signext %x, i1 signext %y) {
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34 entry:
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35 ; ALL-LABEL: tst_select_i1_i1:
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36
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37 ; M2-M3: andi $[[T0:[0-9]+]], $4, 1
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38 ; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
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39 ; M2-M3: nop
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40 ; M2-M3: move $5, $6
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41 ; M2-M3: $[[BB0]]:
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42 ; M2-M3: jr $ra
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43 ; M2-M3: move $2, $5
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44
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45 ; CMOV: andi $[[T0:[0-9]+]], $4, 1
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46 ; CMOV: movn $6, $5, $[[T0]]
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47 ; CMOV: move $2, $6
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48
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49 ; SEL: andi $[[T0:[0-9]+]], $4, 1
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50 ; SEL: seleqz $[[T1:[0-9]+]], $6, $[[T0]]
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51 ; SEL: selnez $[[T2:[0-9]+]], $5, $[[T0]]
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52 ; SEL: or $2, $[[T2]], $[[T1]]
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53 %r = select i1 %s, i1 %x, i1 %y
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54 ret i1 %r
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55 }
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56
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57 define signext i8 @tst_select_i1_i8(i1 signext %s,
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58 i8 signext %x, i8 signext %y) {
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59 entry:
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60 ; ALL-LABEL: tst_select_i1_i8:
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61
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62 ; M2-M3: andi $[[T0:[0-9]+]], $4, 1
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63 ; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
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64 ; M2-M3: nop
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65 ; M2-M3: move $5, $6
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66 ; M2-M3: $[[BB0]]:
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67 ; M2-M3: jr $ra
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68 ; M2-M3: move $2, $5
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69
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70 ; CMOV: andi $[[T0:[0-9]+]], $4, 1
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71 ; CMOV: movn $6, $5, $[[T0]]
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72 ; CMOV: move $2, $6
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73
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74 ; SEL: andi $[[T0:[0-9]+]], $4, 1
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75 ; SEL: seleqz $[[T1:[0-9]+]], $6, $[[T0]]
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76 ; SEL: selnez $[[T2:[0-9]+]], $5, $[[T0]]
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77 ; SEL: or $2, $[[T2]], $[[T1]]
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78 %r = select i1 %s, i8 %x, i8 %y
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79 ret i8 %r
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80 }
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81
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82 define signext i32 @tst_select_i1_i32(i1 signext %s,
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83 i32 signext %x, i32 signext %y) {
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84 entry:
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85 ; ALL-LABEL: tst_select_i1_i32:
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86
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87 ; M2-M3: andi $[[T0:[0-9]+]], $4, 1
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88 ; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
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89 ; M2-M3: nop
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90 ; M2-M3: move $5, $6
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91 ; M2-M3: $[[BB0]]:
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92 ; M2-M3: jr $ra
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93 ; M2-M3: move $2, $5
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94
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95 ; CMOV: andi $[[T0:[0-9]+]], $4, 1
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96 ; CMOV: movn $6, $5, $[[T0]]
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97 ; CMOV: move $2, $6
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98
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99 ; SEL: andi $[[T0:[0-9]+]], $4, 1
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100 ; SEL: seleqz $[[T1:[0-9]+]], $6, $[[T0]]
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101 ; SEL: selnez $[[T2:[0-9]+]], $5, $[[T0]]
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102 ; SEL: or $2, $[[T2]], $[[T1]]
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103 %r = select i1 %s, i32 %x, i32 %y
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104 ret i32 %r
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105 }
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106
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107 define signext i64 @tst_select_i1_i64(i1 signext %s,
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108 i64 signext %x, i64 signext %y) {
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109 entry:
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110 ; ALL-LABEL: tst_select_i1_i64:
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111
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112 ; M2: andi $[[T0:[0-9]+]], $4, 1
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113 ; M2: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
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114 ; M2: nop
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115 ; M2: lw $[[T1:[0-9]+]], 16($sp)
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116 ; M2: $[[BB0]]:
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117 ; FIXME: This branch is redundant
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118 ; M2: bnez $[[T0]], $[[BB1:BB[0-9_]+]]
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119 ; M2: nop
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120 ; M2: lw $[[T2:[0-9]+]], 20($sp)
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121 ; M2: $[[BB1]]:
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122 ; M2: move $2, $[[T1]]
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123 ; M2: jr $ra
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124 ; M2: move $3, $[[T2]]
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125
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126 ; CMOV-32: andi $[[T0:[0-9]+]], $4, 1
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127 ; CMOV-32: lw $2, 16($sp)
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128 ; CMOV-32: movn $2, $6, $[[T0]]
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129 ; CMOV-32: lw $3, 20($sp)
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130 ; CMOV-32: movn $3, $7, $[[T0]]
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131
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132 ; SEL-32: andi $[[T0:[0-9]+]], $4, 1
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133 ; SEL-32: selnez $[[T1:[0-9]+]], $6, $[[T0]]
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134 ; SEL-32: lw $[[T2:[0-9]+]], 16($sp)
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135 ; SEL-32: seleqz $[[T3:[0-9]+]], $[[T2]], $[[T0]]
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136 ; SEL-32: or $2, $[[T1]], $[[T3]]
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137 ; SEL-32: selnez $[[T4:[0-9]+]], $7, $[[T0]]
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138 ; SEL-32: lw $[[T5:[0-9]+]], 20($sp)
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139 ; SEL-32: seleqz $[[T6:[0-9]+]], $[[T5]], $[[T0]]
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140 ; SEL-32: or $3, $[[T4]], $[[T6]]
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141
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142 ; M3: andi $[[T0:[0-9]+]], $4, 1
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143 ; M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
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144 ; M3: nop
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145 ; M3: move $5, $6
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146 ; M3: $[[BB0]]:
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147 ; M3: jr $ra
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148 ; M3: move $2, $5
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149
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150 ; CMOV-64: andi $[[T0:[0-9]+]], $4, 1
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151 ; CMOV-64: movn $6, $5, $[[T0]]
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152 ; CMOV-64: move $2, $6
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153
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154 ; SEL-64: andi $[[T0:[0-9]+]], $4, 1
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155 ; FIXME: This shift is redundant
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156 ; SEL-64: sll $[[T0]], $[[T0]], 0
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157 ; SEL-64: seleqz $[[T1:[0-9]+]], $6, $[[T0]]
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158 ; SEL-64: selnez $[[T0]], $5, $[[T0]]
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159 ; SEL-64: or $2, $[[T0]], $[[T1]]
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160 %r = select i1 %s, i64 %x, i64 %y
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161 ret i64 %r
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162 }
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163
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164 define float @tst_select_i1_float(i1 signext %s, float %x, float %y) {
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165 entry:
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166 ; ALL-LABEL: tst_select_i1_float:
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167
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168 ; M2-M3: andi $[[T0:[0-9]+]], $4, 1
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169 ; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
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170 ; M2-M3: nop
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171 ; M2: jr $ra
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172 ; M2: mtc1 $6, $f0
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173 ; M3: mov.s $f13, $f14
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174 ; M2-M3: $[[BB0]]:
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175 ; M2-M3: jr $ra
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176 ; M2: mtc1 $5, $f0
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177 ; M3: mov.s $f0, $f13
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178
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179 ; CMOV-32: mtc1 $6, $f0
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180 ; CMOV-32: mtc1 $5, $f1
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181 ; CMOV-32: andi $[[T0:[0-9]+]], $4, 1
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182 ; CMOV-32: movn.s $f0, $f1, $[[T0]]
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183
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184 ; SEL-32: mtc1 $5, $[[F0:f[0-9]+]]
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185 ; SEL-32: mtc1 $6, $[[F1:f[0-9]+]]
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186 ; SEL-32: mtc1 $4, $f0
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187 ; SEL-32: sel.s $f0, $[[F1]], $[[F0]]
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188
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189 ; CMOV-64: andi $[[T0:[0-9]+]], $4, 1
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190 ; CMOV-64: movn.s $f14, $f13, $[[T0]]
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191 ; CMOV-64: mov.s $f0, $f14
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192
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193 ; SEL-64: mtc1 $4, $f0
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194 ; SEL-64: sel.s $f0, $f14, $f13
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195 %r = select i1 %s, float %x, float %y
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196 ret float %r
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197 }
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198
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199 define float @tst_select_i1_float_reordered(float %x, float %y,
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200 i1 signext %s) {
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201 entry:
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202 ; ALL-LABEL: tst_select_i1_float_reordered:
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203
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204 ; M2-M3: andi $[[T0:[0-9]+]], $6, 1
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205 ; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
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206 ; M2-M3: nop
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207 ; M2: mov.s $f12, $f14
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208 ; M3: mov.s $f12, $f13
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209 ; M2-M3: $[[BB0]]:
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210 ; M2-M3: jr $ra
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211 ; M2-M3: mov.s $f0, $f12
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212
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213 ; CMOV-32: andi $[[T0:[0-9]+]], $6, 1
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214 ; CMOV-32: movn.s $f14, $f12, $[[T0]]
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215 ; CMOV-32: mov.s $f0, $f14
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216
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217 ; SEL-32: mtc1 $6, $f0
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218 ; SEL-32: sel.s $f0, $f14, $f12
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219
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220 ; CMOV-64: andi $[[T0:[0-9]+]], $6, 1
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221 ; CMOV-64: movn.s $f13, $f12, $[[T0]]
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222 ; CMOV-64: mov.s $f0, $f13
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223
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224 ; SEL-64: mtc1 $6, $f0
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225 ; SEL-64: sel.s $f0, $f13, $f12
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226 %r = select i1 %s, float %x, float %y
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227 ret float %r
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228 }
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229
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230 define double @tst_select_i1_double(i1 signext %s, double %x, double %y) {
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231 entry:
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232 ; ALL-LABEL: tst_select_i1_double:
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233
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234 ; M2: andi $[[T0:[0-9]+]], $4, 1
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235 ; M2: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
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236 ; M2: nop
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237 ; M2: ldc1 $f0, 16($sp)
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238 ; M2: jr $ra
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239 ; M2: nop
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240 ; M2: $[[BB0]]:
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241 ; M2: mtc1 $7, $f0
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242 ; M2: jr $ra
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243 ; M2: mtc1 $6, $f1
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244
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95
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245 ; CMOV-32: mtc1 $7, $[[F0:f[0-9]+]]
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246 ; CMOV-32R1: mtc1 $6, $f{{[0-9]+}}
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247 ; CMOV-32R2-R5: mthc1 $6, $[[F0]]
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248 ; CMOV-32: andi $[[T0:[0-9]+]], $4, 1
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249 ; CMOV-32: ldc1 $f0, 16($sp)
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250 ; CMOV-32: movn.d $f0, $[[F0]], $[[T0]]
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83
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251
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252 ; SEL-32: mtc1 $7, $[[F0:f[0-9]+]]
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253 ; SEL-32: mthc1 $6, $[[F0]]
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254 ; SEL-32: ldc1 $[[F1:f[0-9]+]], 16($sp)
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255 ; SEL-32: mtc1 $4, $f0
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256 ; SEL-32: sel.d $f0, $[[F1]], $[[F0]]
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257
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258 ; M3: andi $[[T0:[0-9]+]], $4, 1
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259 ; M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
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260 ; M3: nop
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261 ; M3: mov.d $f13, $f14
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262 ; M3: $[[BB0]]:
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263 ; M3: jr $ra
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264 ; M3: mov.d $f0, $f13
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265
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266 ; CMOV-64: andi $[[T0:[0-9]+]], $4, 1
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267 ; CMOV-64: movn.d $f14, $f13, $[[T0]]
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268 ; CMOV-64: mov.d $f0, $f14
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269
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270 ; SEL-64: mtc1 $4, $f0
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271 ; SEL-64: sel.d $f0, $f14, $f13
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272 %r = select i1 %s, double %x, double %y
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273 ret double %r
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274 }
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275
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276 define double @tst_select_i1_double_reordered(double %x, double %y,
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277 i1 signext %s) {
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278 entry:
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279 ; ALL-LABEL: tst_select_i1_double_reordered:
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280
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281 ; M2: lw $[[T0:[0-9]+]], 16($sp)
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282 ; M2: andi $[[T1:[0-9]+]], $[[T0]], 1
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283 ; M2: bnez $[[T1]], $[[BB0:BB[0-9_]+]]
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284 ; M2: nop
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285 ; M2: mov.d $f12, $f14
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286 ; M2: $[[BB0]]:
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287 ; M2: jr $ra
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288 ; M2: mov.d $f0, $f12
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289
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290 ; CMOV-32: lw $[[T0:[0-9]+]], 16($sp)
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291 ; CMOV-32: andi $[[T1:[0-9]+]], $[[T0]], 1
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292 ; CMOV-32: movn.d $f14, $f12, $[[T1]]
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293 ; CMOV-32: mov.d $f0, $f14
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294
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295 ; SEL-32: lw $[[T0:[0-9]+]], 16($sp)
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296 ; SEL-32: mtc1 $[[T0]], $f0
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297 ; SEL-32: sel.d $f0, $f14, $f12
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298
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299 ; M3: andi $[[T0:[0-9]+]], $6, 1
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300 ; M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
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301 ; M3: nop
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302 ; M3: mov.d $f12, $f13
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303 ; M3: $[[BB0]]:
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304 ; M3: jr $ra
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305 ; M3: mov.d $f0, $f12
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306
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307 ; CMOV-64: andi $[[T0:[0-9]+]], $6, 1
|
|
|
308 ; CMOV-64: movn.d $f13, $f12, $[[T0]]
|
|
|
309 ; CMOV-64: mov.d $f0, $f13
|
|
|
310
|
|
|
311 ; SEL-64: mtc1 $6, $f0
|
|
|
312 ; SEL-64: sel.d $f0, $f13, $f12
|
|
|
313 %r = select i1 %s, double %x, double %y
|
|
|
314 ret double %r
|
|
|
315 }
|
|
|
316
|
|
|
317 define float @tst_select_fcmp_olt_float(float %x, float %y) {
|
|
|
318 entry:
|
|
|
319 ; ALL-LABEL: tst_select_fcmp_olt_float:
|
|
|
320
|
|
|
321 ; M2: c.olt.s $f12, $f14
|
|
|
322 ; M3: c.olt.s $f12, $f13
|
|
|
323 ; M2-M3: bc1t $[[BB0:BB[0-9_]+]]
|
|
|
324 ; M2-M3: nop
|
|
|
325 ; M2: mov.s $f12, $f14
|
|
|
326 ; M3: mov.s $f12, $f13
|
|
|
327 ; M2-M3: $[[BB0]]:
|
|
|
328 ; M2-M3: jr $ra
|
|
|
329 ; M2-M3: mov.s $f0, $f12
|
|
|
330
|
|
|
331 ; CMOV-32: c.olt.s $f12, $f14
|
|
|
332 ; CMOV-32: movt.s $f14, $f12, $fcc0
|
|
|
333 ; CMOV-32: mov.s $f0, $f14
|
|
|
334
|
|
|
335 ; SEL-32: cmp.lt.s $f0, $f12, $f14
|
|
|
336 ; SEL-32: sel.s $f0, $f14, $f12
|
|
|
337
|
|
|
338 ; CMOV-64: c.olt.s $f12, $f13
|
|
|
339 ; CMOV-64: movt.s $f13, $f12, $fcc0
|
|
|
340 ; CMOV-64: mov.s $f0, $f13
|
|
|
341
|
|
|
342 ; SEL-64: cmp.lt.s $f0, $f12, $f13
|
|
|
343 ; SEL-64: sel.s $f0, $f13, $f12
|
|
|
344 %s = fcmp olt float %x, %y
|
|
|
345 %r = select i1 %s, float %x, float %y
|
|
|
346 ret float %r
|
|
|
347 }
|
|
|
348
|
|
|
349 define float @tst_select_fcmp_ole_float(float %x, float %y) {
|
|
|
350 entry:
|
|
|
351 ; ALL-LABEL: tst_select_fcmp_ole_float:
|
|
|
352
|
|
|
353 ; M2: c.ole.s $f12, $f14
|
|
|
354 ; M3: c.ole.s $f12, $f13
|
|
|
355 ; M2-M3: bc1t $[[BB0:BB[0-9_]+]]
|
|
|
356 ; M2-M3: nop
|
|
|
357 ; M2: mov.s $f12, $f14
|
|
|
358 ; M3: mov.s $f12, $f13
|
|
|
359 ; M2-M3: $[[BB0]]:
|
|
|
360 ; M2-M3: jr $ra
|
|
|
361 ; M2-M3: mov.s $f0, $f12
|
|
|
362
|
|
|
363 ; CMOV-32: c.ole.s $f12, $f14
|
|
|
364 ; CMOV-32: movt.s $f14, $f12, $fcc0
|
|
|
365 ; CMOV-32: mov.s $f0, $f14
|
|
|
366
|
|
|
367 ; SEL-32: cmp.le.s $f0, $f12, $f14
|
|
|
368 ; SEL-32: sel.s $f0, $f14, $f12
|
|
|
369
|
|
|
370 ; CMOV-64: c.ole.s $f12, $f13
|
|
|
371 ; CMOV-64: movt.s $f13, $f12, $fcc0
|
|
|
372 ; CMOV-64: mov.s $f0, $f13
|
|
|
373
|
|
|
374 ; SEL-64: cmp.le.s $f0, $f12, $f13
|
|
|
375 ; SEL-64: sel.s $f0, $f13, $f12
|
|
|
376 %s = fcmp ole float %x, %y
|
|
|
377 %r = select i1 %s, float %x, float %y
|
|
|
378 ret float %r
|
|
|
379 }
|
|
|
380
|
|
|
381 define float @tst_select_fcmp_ogt_float(float %x, float %y) {
|
|
|
382 entry:
|
|
|
383 ; ALL-LABEL: tst_select_fcmp_ogt_float:
|
|
|
384
|
|
|
385 ; M2: c.ule.s $f12, $f14
|
|
|
386 ; M3: c.ule.s $f12, $f13
|
|
|
387 ; M2-M3: bc1f $[[BB0:BB[0-9_]+]]
|
|
|
388 ; M2-M3: nop
|
|
|
389 ; M2: mov.s $f12, $f14
|
|
|
390 ; M3: mov.s $f12, $f13
|
|
|
391 ; M2-M3: $[[BB0]]:
|
|
|
392 ; M2-M3: jr $ra
|
|
|
393 ; M2-M3: mov.s $f0, $f12
|
|
|
394
|
|
|
395 ; CMOV-32: c.ule.s $f12, $f14
|
|
|
396 ; CMOV-32: movf.s $f14, $f12, $fcc0
|
|
|
397 ; CMOV-32: mov.s $f0, $f14
|
|
|
398
|
|
|
399 ; SEL-32: cmp.lt.s $f0, $f14, $f12
|
|
|
400 ; SEL-32: sel.s $f0, $f14, $f12
|
|
|
401
|
|
|
402 ; CMOV-64: c.ule.s $f12, $f13
|
|
|
403 ; CMOV-64: movf.s $f13, $f12, $fcc0
|
|
|
404 ; CMOV-64: mov.s $f0, $f13
|
|
|
405
|
|
|
406 ; SEL-64: cmp.lt.s $f0, $f13, $f12
|
|
|
407 ; SEL-64: sel.s $f0, $f13, $f12
|
|
|
408 %s = fcmp ogt float %x, %y
|
|
|
409 %r = select i1 %s, float %x, float %y
|
|
|
410 ret float %r
|
|
|
411 }
|
|
|
412
|
|
|
413 define float @tst_select_fcmp_oge_float(float %x, float %y) {
|
|
|
414 entry:
|
|
|
415 ; ALL-LABEL: tst_select_fcmp_oge_float:
|
|
|
416
|
|
|
417 ; M2: c.ult.s $f12, $f14
|
|
|
418 ; M3: c.ult.s $f12, $f13
|
|
|
419 ; M2-M3: bc1f $[[BB0:BB[0-9_]+]]
|
|
|
420 ; M2-M3: nop
|
|
|
421 ; M2: mov.s $f12, $f14
|
|
|
422 ; M3: mov.s $f12, $f13
|
|
|
423 ; M2-M3: $[[BB0]]:
|
|
|
424 ; M2-M3: jr $ra
|
|
|
425 ; M2-M3: mov.s $f0, $f12
|
|
|
426
|
|
|
427 ; CMOV-32: c.ult.s $f12, $f14
|
|
|
428 ; CMOV-32: movf.s $f14, $f12, $fcc0
|
|
|
429 ; CMOV-32: mov.s $f0, $f14
|
|
|
430
|
|
|
431 ; SEL-32: cmp.le.s $f0, $f14, $f12
|
|
|
432 ; SEL-32: sel.s $f0, $f14, $f12
|
|
|
433
|
|
|
434 ; CMOV-64: c.ult.s $f12, $f13
|
|
|
435 ; CMOV-64: movf.s $f13, $f12, $fcc0
|
|
|
436 ; CMOV-64: mov.s $f0, $f13
|
|
|
437
|
|
|
438 ; SEL-64: cmp.le.s $f0, $f13, $f12
|
|
|
439 ; SEL-64: sel.s $f0, $f13, $f12
|
|
|
440 %s = fcmp oge float %x, %y
|
|
|
441 %r = select i1 %s, float %x, float %y
|
|
|
442 ret float %r
|
|
|
443 }
|
|
|
444
|
|
|
445 define float @tst_select_fcmp_oeq_float(float %x, float %y) {
|
|
|
446 entry:
|
|
|
447 ; ALL-LABEL: tst_select_fcmp_oeq_float:
|
|
|
448
|
|
|
449 ; M2: c.eq.s $f12, $f14
|
|
|
450 ; M3: c.eq.s $f12, $f13
|
|
|
451 ; M2-M3: bc1t $[[BB0:BB[0-9_]+]]
|
|
|
452 ; M2-M3: nop
|
|
|
453 ; M2: mov.s $f12, $f14
|
|
|
454 ; M3: mov.s $f12, $f13
|
|
|
455 ; M2-M3: $[[BB0]]:
|
|
|
456 ; M2-M3: jr $ra
|
|
|
457 ; M2-M3: mov.s $f0, $f12
|
|
|
458
|
|
|
459 ; CMOV-32: c.eq.s $f12, $f14
|
|
|
460 ; CMOV-32: movt.s $f14, $f12, $fcc0
|
|
|
461 ; CMOV-32: mov.s $f0, $f14
|
|
|
462
|
|
|
463 ; SEL-32: cmp.eq.s $f0, $f12, $f14
|
|
|
464 ; SEL-32: sel.s $f0, $f14, $f12
|
|
|
465
|
|
|
466 ; CMOV-64: c.eq.s $f12, $f13
|
|
|
467 ; CMOV-64: movt.s $f13, $f12, $fcc0
|
|
|
468 ; CMOV-64: mov.s $f0, $f13
|
|
|
469
|
|
|
470 ; SEL-64: cmp.eq.s $f0, $f12, $f13
|
|
|
471 ; SEL-64: sel.s $f0, $f13, $f12
|
|
|
472 %s = fcmp oeq float %x, %y
|
|
|
473 %r = select i1 %s, float %x, float %y
|
|
|
474 ret float %r
|
|
|
475 }
|
|
|
476
|
|
|
477 define float @tst_select_fcmp_one_float(float %x, float %y) {
|
|
|
478 entry:
|
|
|
479 ; ALL-LABEL: tst_select_fcmp_one_float:
|
|
|
480
|
|
|
481 ; M2: c.ueq.s $f12, $f14
|
|
|
482 ; M3: c.ueq.s $f12, $f13
|
|
|
483 ; M2-M3: bc1f $[[BB0:BB[0-9_]+]]
|
|
|
484 ; M2-M3: nop
|
|
|
485 ; M2: mov.s $f12, $f14
|
|
|
486 ; M3: mov.s $f12, $f13
|
|
|
487 ; M2-M3: $[[BB0]]:
|
|
|
488 ; M2-M3: jr $ra
|
|
|
489 ; M2-M3: mov.s $f0, $f12
|
|
|
490
|
|
|
491 ; CMOV-32: c.ueq.s $f12, $f14
|
|
|
492 ; CMOV-32: movf.s $f14, $f12, $fcc0
|
|
|
493 ; CMOV-32: mov.s $f0, $f14
|
|
|
494
|
|
|
495 ; SEL-32: cmp.ueq.s $f0, $f12, $f14
|
|
|
496 ; SEL-32: mfc1 $[[T0:[0-9]+]], $f0
|
|
|
497 ; SEL-32: not $[[T0]], $[[T0]]
|
|
|
498 ; SEL-32: mtc1 $[[T0:[0-9]+]], $f0
|
|
|
499 ; SEL-32: sel.s $f0, $f14, $f12
|
|
|
500
|
|
|
501 ; CMOV-64: c.ueq.s $f12, $f13
|
|
|
502 ; CMOV-64: movf.s $f13, $f12, $fcc0
|
|
|
503 ; CMOV-64: mov.s $f0, $f13
|
|
|
504
|
|
|
505 ; SEL-64: cmp.ueq.s $f0, $f12, $f13
|
|
|
506 ; SEL-64: mfc1 $[[T0:[0-9]+]], $f0
|
|
|
507 ; SEL-64: not $[[T0]], $[[T0]]
|
|
|
508 ; SEL-64: mtc1 $[[T0:[0-9]+]], $f0
|
|
|
509 ; SEL-64: sel.s $f0, $f13, $f12
|
|
|
510
|
|
|
511 %s = fcmp one float %x, %y
|
|
|
512 %r = select i1 %s, float %x, float %y
|
|
|
513 ret float %r
|
|
|
514 }
|
|
|
515
|
|
|
516 define double @tst_select_fcmp_olt_double(double %x, double %y) {
|
|
|
517 entry:
|
|
|
518 ; ALL-LABEL: tst_select_fcmp_olt_double:
|
|
|
519
|
|
|
520 ; M2: c.olt.d $f12, $f14
|
|
|
521 ; M3: c.olt.d $f12, $f13
|
|
|
522 ; M2-M3: bc1t $[[BB0:BB[0-9_]+]]
|
|
|
523 ; M2-M3: nop
|
|
|
524 ; M2: mov.d $f12, $f14
|
|
|
525 ; M3: mov.d $f12, $f13
|
|
|
526 ; M2-M3: $[[BB0]]:
|
|
|
527 ; M2-M3: jr $ra
|
|
|
528 ; M2-M3: mov.d $f0, $f12
|
|
|
529
|
|
|
530 ; CMOV-32: c.olt.d $f12, $f14
|
|
|
531 ; CMOV-32: movt.d $f14, $f12, $fcc0
|
|
|
532 ; CMOV-32: mov.d $f0, $f14
|
|
|
533
|
|
|
534 ; SEL-32: cmp.lt.d $f0, $f12, $f14
|
|
|
535 ; SEL-32: sel.d $f0, $f14, $f12
|
|
|
536
|
|
|
537 ; CMOV-64: c.olt.d $f12, $f13
|
|
|
538 ; CMOV-64: movt.d $f13, $f12, $fcc0
|
|
|
539 ; CMOV-64: mov.d $f0, $f13
|
|
|
540
|
|
|
541 ; SEL-64: cmp.lt.d $f0, $f12, $f13
|
|
|
542 ; SEL-64: sel.d $f0, $f13, $f12
|
|
|
543 %s = fcmp olt double %x, %y
|
|
|
544 %r = select i1 %s, double %x, double %y
|
|
|
545 ret double %r
|
|
|
546 }
|
|
|
547
|
|
|
548 define double @tst_select_fcmp_ole_double(double %x, double %y) {
|
|
|
549 entry:
|
|
|
550 ; ALL-LABEL: tst_select_fcmp_ole_double:
|
|
|
551
|
|
|
552 ; M2: c.ole.d $f12, $f14
|
|
|
553 ; M3: c.ole.d $f12, $f13
|
|
|
554 ; M2-M3: bc1t $[[BB0:BB[0-9_]+]]
|
|
|
555 ; M2-M3: nop
|
|
|
556 ; M2: mov.d $f12, $f14
|
|
|
557 ; M3: mov.d $f12, $f13
|
|
|
558 ; M2-M3: $[[BB0]]:
|
|
|
559 ; M2-M3: jr $ra
|
|
|
560 ; M2-M3: mov.d $f0, $f12
|
|
|
561
|
|
|
562 ; CMOV-32: c.ole.d $f12, $f14
|
|
|
563 ; CMOV-32: movt.d $f14, $f12, $fcc0
|
|
|
564 ; CMOV-32: mov.d $f0, $f14
|
|
|
565
|
|
|
566 ; SEL-32: cmp.le.d $f0, $f12, $f14
|
|
|
567 ; SEL-32: sel.d $f0, $f14, $f12
|
|
|
568
|
|
|
569 ; CMOV-64: c.ole.d $f12, $f13
|
|
|
570 ; CMOV-64: movt.d $f13, $f12, $fcc0
|
|
|
571 ; CMOV-64: mov.d $f0, $f13
|
|
|
572
|
|
|
573 ; SEL-64: cmp.le.d $f0, $f12, $f13
|
|
|
574 ; SEL-64: sel.d $f0, $f13, $f12
|
|
|
575 %s = fcmp ole double %x, %y
|
|
|
576 %r = select i1 %s, double %x, double %y
|
|
|
577 ret double %r
|
|
|
578 }
|
|
|
579
|
|
|
580 define double @tst_select_fcmp_ogt_double(double %x, double %y) {
|
|
|
581 entry:
|
|
|
582 ; ALL-LABEL: tst_select_fcmp_ogt_double:
|
|
|
583
|
|
|
584 ; M2: c.ule.d $f12, $f14
|
|
|
585 ; M3: c.ule.d $f12, $f13
|
|
|
586 ; M2-M3: bc1f $[[BB0:BB[0-9_]+]]
|
|
|
587 ; M2-M3: nop
|
|
|
588 ; M2: mov.d $f12, $f14
|
|
|
589 ; M3: mov.d $f12, $f13
|
|
|
590 ; M2-M3: $[[BB0]]:
|
|
|
591 ; M2-M3: jr $ra
|
|
|
592 ; M2-M3: mov.d $f0, $f12
|
|
|
593
|
|
|
594 ; CMOV-32: c.ule.d $f12, $f14
|
|
|
595 ; CMOV-32: movf.d $f14, $f12, $fcc0
|
|
|
596 ; CMOV-32: mov.d $f0, $f14
|
|
|
597
|
|
|
598 ; SEL-32: cmp.lt.d $f0, $f14, $f12
|
|
|
599 ; SEL-32: sel.d $f0, $f14, $f12
|
|
|
600
|
|
|
601 ; CMOV-64: c.ule.d $f12, $f13
|
|
|
602 ; CMOV-64: movf.d $f13, $f12, $fcc0
|
|
|
603 ; CMOV-64: mov.d $f0, $f13
|
|
|
604
|
|
|
605 ; SEL-64: cmp.lt.d $f0, $f13, $f12
|
|
|
606 ; SEL-64: sel.d $f0, $f13, $f12
|
|
|
607 %s = fcmp ogt double %x, %y
|
|
|
608 %r = select i1 %s, double %x, double %y
|
|
|
609 ret double %r
|
|
|
610 }
|
|
|
611
|
|
|
612 define double @tst_select_fcmp_oge_double(double %x, double %y) {
|
|
|
613 entry:
|
|
|
614 ; ALL-LABEL: tst_select_fcmp_oge_double:
|
|
|
615
|
|
|
616 ; M2: c.ult.d $f12, $f14
|
|
|
617 ; M3: c.ult.d $f12, $f13
|
|
|
618 ; M2-M3: bc1f $[[BB0:BB[0-9_]+]]
|
|
|
619 ; M2-M3: nop
|
|
|
620 ; M2: mov.d $f12, $f14
|
|
|
621 ; M3: mov.d $f12, $f13
|
|
|
622 ; M2-M3: $[[BB0]]:
|
|
|
623 ; M2-M3: jr $ra
|
|
|
624 ; M2-M3: mov.d $f0, $f12
|
|
|
625
|
|
|
626 ; CMOV-32: c.ult.d $f12, $f14
|
|
|
627 ; CMOV-32: movf.d $f14, $f12, $fcc0
|
|
|
628 ; CMOV-32: mov.d $f0, $f14
|
|
|
629
|
|
|
630 ; SEL-32: cmp.le.d $f0, $f14, $f12
|
|
|
631 ; SEL-32: sel.d $f0, $f14, $f12
|
|
|
632
|
|
|
633 ; CMOV-64: c.ult.d $f12, $f13
|
|
|
634 ; CMOV-64: movf.d $f13, $f12, $fcc0
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635 ; CMOV-64: mov.d $f0, $f13
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636
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637 ; SEL-64: cmp.le.d $f0, $f13, $f12
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638 ; SEL-64: sel.d $f0, $f13, $f12
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639 %s = fcmp oge double %x, %y
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640 %r = select i1 %s, double %x, double %y
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641 ret double %r
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642 }
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643
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644 define double @tst_select_fcmp_oeq_double(double %x, double %y) {
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645 entry:
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646 ; ALL-LABEL: tst_select_fcmp_oeq_double:
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647
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648 ; M2: c.eq.d $f12, $f14
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649 ; M3: c.eq.d $f12, $f13
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650 ; M2-M3: bc1t $[[BB0:BB[0-9_]+]]
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651 ; M2-M3: nop
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652 ; M2: mov.d $f12, $f14
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653 ; M3: mov.d $f12, $f13
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654 ; M2-M3: $[[BB0]]:
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655 ; M2-M3: jr $ra
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656 ; M2-M3: mov.d $f0, $f12
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657
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658 ; CMOV-32: c.eq.d $f12, $f14
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659 ; CMOV-32: movt.d $f14, $f12, $fcc0
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660 ; CMOV-32: mov.d $f0, $f14
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661
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662 ; SEL-32: cmp.eq.d $f0, $f12, $f14
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663 ; SEL-32: sel.d $f0, $f14, $f12
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664
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665 ; CMOV-64: c.eq.d $f12, $f13
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666 ; CMOV-64: movt.d $f13, $f12, $fcc0
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667 ; CMOV-64: mov.d $f0, $f13
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668
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669 ; SEL-64: cmp.eq.d $f0, $f12, $f13
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670 ; SEL-64: sel.d $f0, $f13, $f12
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671 %s = fcmp oeq double %x, %y
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672 %r = select i1 %s, double %x, double %y
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673 ret double %r
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674 }
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675
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676 define double @tst_select_fcmp_one_double(double %x, double %y) {
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677 entry:
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678 ; ALL-LABEL: tst_select_fcmp_one_double:
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679
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680 ; M2: c.ueq.d $f12, $f14
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681 ; M3: c.ueq.d $f12, $f13
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682 ; M2-M3: bc1f $[[BB0:BB[0-9_]+]]
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683 ; M2-M3: nop
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684 ; M2: mov.d $f12, $f14
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685 ; M3: mov.d $f12, $f13
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686 ; M2-M3: $[[BB0]]:
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687 ; M2-M3: jr $ra
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688 ; M2-M3: mov.d $f0, $f12
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689
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690 ; CMOV-32: c.ueq.d $f12, $f14
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691 ; CMOV-32: movf.d $f14, $f12, $fcc0
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692 ; CMOV-32: mov.d $f0, $f14
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693
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694 ; SEL-32: cmp.ueq.d $f0, $f12, $f14
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695 ; SEL-32: mfc1 $[[T0:[0-9]+]], $f0
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696 ; SEL-32: not $[[T0]], $[[T0]]
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697 ; SEL-32: mtc1 $[[T0:[0-9]+]], $f0
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698 ; SEL-32: sel.d $f0, $f14, $f12
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699
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700 ; CMOV-64: c.ueq.d $f12, $f13
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701 ; CMOV-64: movf.d $f13, $f12, $fcc0
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702 ; CMOV-64: mov.d $f0, $f13
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703
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704 ; SEL-64: cmp.ueq.d $f0, $f12, $f13
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705 ; SEL-64: mfc1 $[[T0:[0-9]+]], $f0
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706 ; SEL-64: not $[[T0]], $[[T0]]
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707 ; SEL-64: mtc1 $[[T0:[0-9]+]], $f0
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708 ; SEL-64: sel.d $f0, $f13, $f12
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709 %s = fcmp one double %x, %y
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710 %r = select i1 %s, double %x, double %y
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711 ret double %r
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712 }
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