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77
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1 ; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS32 -check-prefix=MIPS32-EL %s
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2 ; RUN: llc -march=mips -mcpu=mips32 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS32 -check-prefix=MIPS32-EB %s
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3 ; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS32 -check-prefix=MIPS32-EL %s
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4 ; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS32 -check-prefix=MIPS32-EB %s
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5 ; RUN: llc -march=mipsel -mcpu=mips32r6 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS32R6 -check-prefix=MIPS32R6-EL %s
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6 ; RUN: llc -march=mips -mcpu=mips32r6 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS32R6 -check-prefix=MIPS32R6-EB %s
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95
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7 ; RUN: llc -march=mips64el -mcpu=mips4 -target-abi=n64 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64 -check-prefix=MIPS64-EL %s
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8 ; RUN: llc -march=mips64 -mcpu=mips4 -target-abi=n64 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64 -check-prefix=MIPS64-EB %s
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9 ; RUN: llc -march=mips64el -mcpu=mips64 -target-abi=n64 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64 -check-prefix=MIPS64-EL %s
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10 ; RUN: llc -march=mips64 -mcpu=mips64 -target-abi=n64 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64 -check-prefix=MIPS64-EB %s
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11 ; RUN: llc -march=mips64el -mcpu=mips64r2 -target-abi=n64 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64 -check-prefix=MIPS64-EL %s
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12 ; RUN: llc -march=mips64 -mcpu=mips64r2 -target-abi=n64 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64 -check-prefix=MIPS64-EB %s
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13 ; RUN: llc -march=mips64el -mcpu=mips64r6 -target-abi=n64 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64R6 -check-prefix=MIPS64R6-EL %s
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14 ; RUN: llc -march=mips64 -mcpu=mips64r6 -target-abi=n64 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64R6 -check-prefix=MIPS64R6-EB %s
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parents:
diff
changeset
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15
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77
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16 %struct.SLL = type { i64 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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17 %struct.SI = type { i32 }
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77
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18 %struct.SUI = type { i32 }
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19
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77
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20 @sll = common global %struct.SLL zeroinitializer, align 1
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21 @si = common global %struct.SI zeroinitializer, align 1
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22 @sui = common global %struct.SUI zeroinitializer, align 1
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23
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24 define i32 @load_SI() nounwind readonly {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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changeset
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25 entry:
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77
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26 ; ALL-LABEL: load_SI:
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27
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28 ; MIPS32-EL: lwl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]])
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29 ; MIPS32-EL: lwr $[[R0]], 0($[[R1]])
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30
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31 ; MIPS32-EB: lwl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
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32 ; MIPS32-EB: lwr $[[R0]], 3($[[R1]])
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33
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34 ; MIPS32R6: lw $[[PTR:[0-9]+]], %got(si)(
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35 ; MIPS32R6: lw $2, 0($[[PTR]])
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36
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37 ; MIPS64-EL: lwl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]])
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38 ; MIPS64-EL: lwr $[[R0]], 0($[[R1]])
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39
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40 ; MIPS64-EB: lwl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
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41 ; MIPS64-EB: lwr $[[R0]], 3($[[R1]])
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42
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43 ; MIPS64R6: ld $[[PTR:[0-9]+]], %got_disp(si)(
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44 ; MIPS64R6: lw $2, 0($[[PTR]])
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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45
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95
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46 %0 = load i32, i32* getelementptr inbounds (%struct.SI, %struct.SI* @si, i32 0, i32 0), align 1
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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47 ret i32 %0
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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48 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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49
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83
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50 define void @store_SI(i32 signext %a) nounwind {
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parents:
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changeset
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51 entry:
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77
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52 ; ALL-LABEL: store_SI:
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53
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54 ; MIPS32-EL: swl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]])
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55 ; MIPS32-EL: swr $[[R0]], 0($[[R1]])
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56
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57 ; MIPS32-EB: swl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
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58 ; MIPS32-EB: swr $[[R0]], 3($[[R1]])
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59
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60 ; MIPS32R6: lw $[[PTR:[0-9]+]], %got(si)(
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61 ; MIPS32R6: sw $4, 0($[[PTR]])
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62
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63 ; MIPS64-EL: swl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]])
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64 ; MIPS64-EL: swr $[[R0]], 0($[[R1]])
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65
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66 ; MIPS64-EB: swl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
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67 ; MIPS64-EB: swr $[[R0]], 3($[[R1]])
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68
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69 ; MIPS64R6: ld $[[PTR:[0-9]+]], %got_disp(si)(
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70 ; MIPS64R6: sw $4, 0($[[PTR]])
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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changeset
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71
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95
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72 store i32 %a, i32* getelementptr inbounds (%struct.SI, %struct.SI* @si, i32 0, i32 0), align 1
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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73 ret void
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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74 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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changeset
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75
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77
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76 define i64 @load_SLL() nounwind readonly {
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77 entry:
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78 ; ALL-LABEL: load_SLL:
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79
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80 ; MIPS32-EL: lwl $2, 3($[[R1:[0-9]+]])
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81 ; MIPS32-EL: lwr $2, 0($[[R1]])
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82 ; MIPS32-EL: lwl $3, 7($[[R1:[0-9]+]])
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83 ; MIPS32-EL: lwr $3, 4($[[R1]])
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84
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85 ; MIPS32-EB: lwl $2, 0($[[R1:[0-9]+]])
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86 ; MIPS32-EB: lwr $2, 3($[[R1]])
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87 ; MIPS32-EB: lwl $3, 4($[[R1:[0-9]+]])
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88 ; MIPS32-EB: lwr $3, 7($[[R1]])
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89
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90 ; MIPS32R6: lw $[[PTR:[0-9]+]], %got(sll)(
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91 ; MIPS32R6-DAG: lw $2, 0($[[PTR]])
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92 ; MIPS32R6-DAG: lw $3, 4($[[PTR]])
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93
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94 ; MIPS64-EL: ldl $[[R0:[0-9]+]], 7($[[R1:[0-9]+]])
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95 ; MIPS64-EL: ldr $[[R0]], 0($[[R1]])
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96
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97 ; MIPS64-EB: ldl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
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98 ; MIPS64-EB: ldr $[[R0]], 7($[[R1]])
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99
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100 ; MIPS64R6: ld $[[PTR:[0-9]+]], %got_disp(sll)(
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101 ; MIPS64R6: ld $2, 0($[[PTR]])
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102
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95
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103 %0 = load i64, i64* getelementptr inbounds (%struct.SLL, %struct.SLL* @sll, i64 0, i32 0), align 1
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77
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104 ret i64 %0
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105 }
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106
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107 define i64 @load_SI_sext_to_i64() nounwind readonly {
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108 entry:
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109 ; ALL-LABEL: load_SI_sext_to_i64:
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110
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111 ; MIPS32-EL: lwl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]])
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112 ; MIPS32-EL: lwr $[[R0]], 0($[[R1]])
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113
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114 ; MIPS32-EB: lwl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
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115 ; MIPS32-EB: lwr $[[R0]], 3($[[R1]])
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116
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117 ; MIPS32R6: lw $[[PTR:[0-9]+]], %got(si)(
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118 ; MIPS32R6-EL: lw $2, 0($[[PTR]])
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119 ; MIPS32R6-EL: sra $3, $2, 31
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120 ; MIPS32R6-EB: lw $3, 0($[[PTR]])
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121 ; MIPS32R6-EB: sra $2, $3, 31
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122
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123 ; MIPS64-EL: lwl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]])
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124 ; MIPS64-EL: lwr $[[R0]], 0($[[R1]])
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125
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126 ; MIPS64-EB: lwl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
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127 ; MIPS64-EB: lwr $[[R0]], 3($[[R1]])
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128
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129 ; MIPS64R6: ld $[[PTR:[0-9]+]], %got_disp(si)(
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130 ; MIPS64R6: lw $2, 0($[[PTR]])
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131
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95
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132 %0 = load i32, i32* getelementptr inbounds (%struct.SI, %struct.SI* @si, i64 0, i32 0), align 1
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77
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133 %conv = sext i32 %0 to i64
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134 ret i64 %conv
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135 }
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136
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137 define i64 @load_UI() nounwind readonly {
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138 entry:
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139 ; ALL-LABEL: load_UI:
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140
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141 ; MIPS32-EL-DAG: lwl $[[R2:2]], 3($[[R1:[0-9]+]])
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142 ; MIPS32-EL-DAG: lwr $[[R2]], 0($[[R1]])
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143 ; MIPS32-EL-DAG: addiu $3, $zero, 0
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144
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145 ; MIPS32-EB-DAG: lwl $[[R2:3]], 0($[[R1:[0-9]+]])
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146 ; MIPS32-EB-DAG: lwr $[[R2]], 3($[[R1]])
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147 ; MIPS32-EB-DAG: addiu $2, $zero, 0
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148
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149 ; MIPS32R6: lw $[[PTR:[0-9]+]], %got(sui)(
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150 ; MIPS32R6-EL-DAG: lw $2, 0($[[PTR]])
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151 ; MIPS32R6-EL-DAG: addiu $3, $zero, 0
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152 ; MIPS32R6-EB-DAG: lw $3, 0($[[PTR]])
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153 ; MIPS32R6-EB-DAG: addiu $2, $zero, 0
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154
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155 ; MIPS64-EL-DAG: lwl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]])
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156 ; MIPS64-EL-DAG: lwr $[[R0]], 0($[[R1]])
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157 ; MIPS64-EL-DAG: daddiu $[[R2:[0-9]+]], $zero, 1
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158 ; MIPS64-EL-DAG: dsll $[[R3:[0-9]+]], $[[R2]], 32
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159 ; MIPS64-EL-DAG: daddiu $[[R4:[0-9]+]], $[[R3]], -1
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160 ; MIPS64-EL-DAG: and ${{[0-9]+}}, $[[R0]], $[[R4]]
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161
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162 ; MIPS64-EB: lwl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
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163 ; MIPS64-EB: lwr $[[R0]], 3($[[R1]])
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164
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165 ; MIPS64R6: ld $[[PTR:[0-9]+]], %got_disp(sui)(
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166 ; MIPS64R6: lwu $2, 0($[[PTR]])
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167
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95
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168 %0 = load i32, i32* getelementptr inbounds (%struct.SUI, %struct.SUI* @sui, i64 0, i32 0), align 1
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77
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169 %conv = zext i32 %0 to i64
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170 ret i64 %conv
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171 }
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172
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173 define void @store_SLL(i64 %a) nounwind {
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174 entry:
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175 ; ALL-LABEL: store_SLL:
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176
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177 ; MIPS32-EL-DAG: swl $[[A1:4]], 3($[[R1:[0-9]+]])
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178 ; MIPS32-EL-DAG: swr $[[A1]], 0($[[R1]])
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179 ; MIPS32-EL-DAG: swl $[[A2:5]], 7($[[R1:[0-9]+]])
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180 ; MIPS32-EL-DAG: swr $[[A2]], 4($[[R1]])
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181
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182 ; MIPS32-EB-DAG: swl $[[A1:4]], 0($[[R1:[0-9]+]])
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183 ; MIPS32-EB-DAG: swr $[[A1]], 3($[[R1]])
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184 ; MIPS32-EB-DAG: swl $[[A1:5]], 4($[[R1:[0-9]+]])
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185 ; MIPS32-EB-DAG: swr $[[A1]], 7($[[R1]])
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186
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187 ; MIPS32R6-DAG: lw $[[PTR:[0-9]+]], %got(sll)(
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188 ; MIPS32R6-DAG: sw $4, 0($[[PTR]])
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189 ; MIPS32R6-DAG: sw $5, 4($[[PTR]])
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190
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191 ; MIPS64-EL: sdl $[[R0:[0-9]+]], 7($[[R1:[0-9]+]])
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192 ; MIPS64-EL: sdr $[[R0]], 0($[[R1]])
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193
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194 ; MIPS64-EB: sdl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
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195 ; MIPS64-EB: sdr $[[R0]], 7($[[R1]])
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196
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197 ; MIPS64R6: ld $[[PTR:[0-9]+]], %got_disp(sll)(
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198 ; MIPS64R6: sd $4, 0($[[PTR]])
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199
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95
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200 store i64 %a, i64* getelementptr inbounds (%struct.SLL, %struct.SLL* @sll, i64 0, i32 0), align 1
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77
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201 ret void
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202 }
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203
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83
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204 define void @store_SI_trunc_from_i64(i32 signext %a) nounwind {
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77
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205 entry:
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206 ; ALL-LABEL: store_SI_trunc_from_i64:
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207
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208 ; MIPS32-EL: swl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]])
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209 ; MIPS32-EL: swr $[[R0]], 0($[[R1]])
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210
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211 ; MIPS32-EB: swl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
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212 ; MIPS32-EB: swr $[[R0]], 3($[[R1]])
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213
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214 ; MIPS32R6: lw $[[PTR:[0-9]+]], %got(si)(
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215 ; MIPS32R6: sw $4, 0($[[PTR]])
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216
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217 ; MIPS64-EL: swl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]])
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218 ; MIPS64-EL: swr $[[R0]], 0($[[R1]])
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219
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220 ; MIPS64-EB: swl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
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221 ; MIPS64-EB: swr $[[R0]], 3($[[R1]])
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222
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223 ; MIPS64R6: ld $[[PTR:[0-9]+]], %got_disp(si)(
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224 ; MIPS64R6: sw $4, 0($[[PTR]])
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225
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95
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226 store i32 %a, i32* getelementptr inbounds (%struct.SI, %struct.SI* @si, i64 0, i32 0), align 1
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77
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227 ret void
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228 }
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229
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230 ;
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231 ; Structures are simply concatenations of the members. They are unaffected by
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232 ; endianness
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233 ;
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234
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235 %struct.S0 = type { i8, i8 }
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236 @struct_s0 = common global %struct.S0 zeroinitializer, align 1
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237 %struct.S1 = type { i16, i16 }
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238 @struct_s1 = common global %struct.S1 zeroinitializer, align 1
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239 %struct.S2 = type { i32, i32 }
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240 @struct_s2 = common global %struct.S2 zeroinitializer, align 1
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241
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242 define void @copy_struct_S0() nounwind {
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243 entry:
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244 ; ALL-LABEL: copy_struct_S0:
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245
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246 ; MIPS32-EL: lw $[[PTR:[0-9]+]], %got(struct_s0)(
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247 ; MIPS32-EB: lw $[[PTR:[0-9]+]], %got(struct_s0)(
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248 ; MIPS32R6: lw $[[PTR:[0-9]+]], %got(struct_s0)(
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249 ; MIPS64-EL: ld $[[PTR:[0-9]+]], %got_disp(struct_s0)(
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250 ; MIPS64-EB: ld $[[PTR:[0-9]+]], %got_disp(struct_s0)(
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251 ; MIPS64R6: ld $[[PTR:[0-9]+]], %got_disp(struct_s0)(
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252
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253 ; FIXME: We should be able to do better than this on MIPS32r6/MIPS64r6 since
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254 ; we have unaligned halfword load/store available
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255 ; ALL-DAG: lbu $[[R1:[0-9]+]], 0($[[PTR]])
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256 ; ALL-DAG: sb $[[R1]], 2($[[PTR]])
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257 ; ALL-DAG: lbu $[[R1:[0-9]+]], 1($[[PTR]])
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258 ; ALL-DAG: sb $[[R1]], 3($[[PTR]])
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259
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95
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260 %0 = load %struct.S0, %struct.S0* getelementptr inbounds (%struct.S0, %struct.S0* @struct_s0, i32 0), align 1
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261 store %struct.S0 %0, %struct.S0* getelementptr inbounds (%struct.S0, %struct.S0* @struct_s0, i32 1), align 1
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77
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262 ret void
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263 }
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264
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265 define void @copy_struct_S1() nounwind {
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266 entry:
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267 ; ALL-LABEL: copy_struct_S1:
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268
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269 ; MIPS32-EL: lw $[[PTR:[0-9]+]], %got(struct_s1)(
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270 ; MIPS32-EB: lw $[[PTR:[0-9]+]], %got(struct_s1)(
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271 ; MIPS32-DAG: lbu $[[R1:[0-9]+]], 0($[[PTR]])
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272 ; MIPS32-DAG: sb $[[R1]], 4($[[PTR]])
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273 ; MIPS32-DAG: lbu $[[R1:[0-9]+]], 1($[[PTR]])
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274 ; MIPS32-DAG: sb $[[R1]], 5($[[PTR]])
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275 ; MIPS32-DAG: lbu $[[R1:[0-9]+]], 2($[[PTR]])
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276 ; MIPS32-DAG: sb $[[R1]], 6($[[PTR]])
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277 ; MIPS32-DAG: lbu $[[R1:[0-9]+]], 3($[[PTR]])
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278 ; MIPS32-DAG: sb $[[R1]], 7($[[PTR]])
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279
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280 ; MIPS32R6: lw $[[PTR:[0-9]+]], %got(struct_s1)(
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281 ; MIPS32R6-DAG: lhu $[[R1:[0-9]+]], 0($[[PTR]])
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282 ; MIPS32R6-DAG: sh $[[R1]], 4($[[PTR]])
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283 ; MIPS32R6-DAG: lhu $[[R1:[0-9]+]], 2($[[PTR]])
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284 ; MIPS32R6-DAG: sh $[[R1]], 6($[[PTR]])
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285
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286 ; MIPS64-EL: ld $[[PTR:[0-9]+]], %got_disp(struct_s1)(
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287 ; MIPS64-EB: ld $[[PTR:[0-9]+]], %got_disp(struct_s1)(
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288 ; MIPS64-DAG: lbu $[[R1:[0-9]+]], 0($[[PTR]])
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289 ; MIPS64-DAG: sb $[[R1]], 4($[[PTR]])
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290 ; MIPS64-DAG: lbu $[[R1:[0-9]+]], 1($[[PTR]])
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291 ; MIPS64-DAG: sb $[[R1]], 5($[[PTR]])
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292 ; MIPS64-DAG: lbu $[[R1:[0-9]+]], 2($[[PTR]])
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293 ; MIPS64-DAG: sb $[[R1]], 6($[[PTR]])
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294 ; MIPS64-DAG: lbu $[[R1:[0-9]+]], 3($[[PTR]])
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295 ; MIPS64-DAG: sb $[[R1]], 7($[[PTR]])
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296
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297 ; MIPS64R6: ld $[[PTR:[0-9]+]], %got_disp(struct_s1)(
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298 ; MIPS64R6-DAG: lhu $[[R1:[0-9]+]], 0($[[PTR]])
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299 ; MIPS64R6-DAG: sh $[[R1]], 4($[[PTR]])
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300 ; MIPS64R6-DAG: lhu $[[R1:[0-9]+]], 2($[[PTR]])
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301 ; MIPS64R6-DAG: sh $[[R1]], 6($[[PTR]])
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302
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95
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303 %0 = load %struct.S1, %struct.S1* getelementptr inbounds (%struct.S1, %struct.S1* @struct_s1, i32 0), align 1
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304 store %struct.S1 %0, %struct.S1* getelementptr inbounds (%struct.S1, %struct.S1* @struct_s1, i32 1), align 1
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77
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305 ret void
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306 }
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307
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308 define void @copy_struct_S2() nounwind {
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309 entry:
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310 ; ALL-LABEL: copy_struct_S2:
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311
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312 ; MIPS32-EL: lw $[[PTR:[0-9]+]], %got(struct_s2)(
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313 ; MIPS32-EL-DAG: lwl $[[R1:[0-9]+]], 3($[[PTR]])
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314 ; MIPS32-EL-DAG: lwr $[[R1]], 0($[[PTR]])
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315 ; MIPS32-EL-DAG: swl $[[R1]], 11($[[PTR]])
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316 ; MIPS32-EL-DAG: swr $[[R1]], 8($[[PTR]])
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317 ; MIPS32-EL-DAG: lwl $[[R1:[0-9]+]], 7($[[PTR]])
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318 ; MIPS32-EL-DAG: lwr $[[R1]], 4($[[PTR]])
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319 ; MIPS32-EL-DAG: swl $[[R1]], 15($[[PTR]])
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320 ; MIPS32-EL-DAG: swr $[[R1]], 12($[[PTR]])
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321
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322 ; MIPS32-EB: lw $[[PTR:[0-9]+]], %got(struct_s2)(
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323 ; MIPS32-EB-DAG: lwl $[[R1:[0-9]+]], 0($[[PTR]])
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324 ; MIPS32-EB-DAG: lwr $[[R1]], 3($[[PTR]])
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325 ; MIPS32-EB-DAG: swl $[[R1]], 8($[[PTR]])
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326 ; MIPS32-EB-DAG: swr $[[R1]], 11($[[PTR]])
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327 ; MIPS32-EB-DAG: lwl $[[R1:[0-9]+]], 4($[[PTR]])
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328 ; MIPS32-EB-DAG: lwr $[[R1]], 7($[[PTR]])
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329 ; MIPS32-EB-DAG: swl $[[R1]], 12($[[PTR]])
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330 ; MIPS32-EB-DAG: swr $[[R1]], 15($[[PTR]])
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331
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332 ; MIPS32R6: lw $[[PTR:[0-9]+]], %got(struct_s2)(
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333 ; MIPS32R6-DAG: lw $[[R1:[0-9]+]], 0($[[PTR]])
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334 ; MIPS32R6-DAG: sw $[[R1]], 8($[[PTR]])
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335 ; MIPS32R6-DAG: lw $[[R1:[0-9]+]], 4($[[PTR]])
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336 ; MIPS32R6-DAG: sw $[[R1]], 12($[[PTR]])
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337
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338 ; MIPS64-EL: ld $[[PTR:[0-9]+]], %got_disp(struct_s2)(
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339 ; MIPS64-EL-DAG: lwl $[[R1:[0-9]+]], 3($[[PTR]])
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340 ; MIPS64-EL-DAG: lwr $[[R1]], 0($[[PTR]])
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341 ; MIPS64-EL-DAG: swl $[[R1]], 11($[[PTR]])
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342 ; MIPS64-EL-DAG: swr $[[R1]], 8($[[PTR]])
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343 ; MIPS64-EL-DAG: lwl $[[R1:[0-9]+]], 7($[[PTR]])
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344 ; MIPS64-EL-DAG: lwr $[[R1]], 4($[[PTR]])
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345 ; MIPS64-EL-DAG: swl $[[R1]], 15($[[PTR]])
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346 ; MIPS64-EL-DAG: swr $[[R1]], 12($[[PTR]])
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347
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348 ; MIPS64-EB: ld $[[PTR:[0-9]+]], %got_disp(struct_s2)(
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349 ; MIPS64-EB-DAG: lwl $[[R1:[0-9]+]], 0($[[PTR]])
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350 ; MIPS64-EB-DAG: lwr $[[R1]], 3($[[PTR]])
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351 ; MIPS64-EB-DAG: swl $[[R1]], 8($[[PTR]])
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352 ; MIPS64-EB-DAG: swr $[[R1]], 11($[[PTR]])
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353 ; MIPS64-EB-DAG: lwl $[[R1:[0-9]+]], 4($[[PTR]])
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354 ; MIPS64-EB-DAG: lwr $[[R1]], 7($[[PTR]])
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355 ; MIPS64-EB-DAG: swl $[[R1]], 12($[[PTR]])
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356 ; MIPS64-EB-DAG: swr $[[R1]], 15($[[PTR]])
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357
|
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|
358 ; MIPS64R6: ld $[[PTR:[0-9]+]], %got_disp(struct_s2)(
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|
359 ; MIPS64R6-DAG: lw $[[R1:[0-9]+]], 0($[[PTR]])
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360 ; MIPS64R6-DAG: sw $[[R1]], 8($[[PTR]])
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361 ; MIPS64R6-DAG: lw $[[R1:[0-9]+]], 4($[[PTR]])
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362 ; MIPS64R6-DAG: sw $[[R1]], 12($[[PTR]])
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|
|
363
|
|
95
|
364 %0 = load %struct.S2, %struct.S2* getelementptr inbounds (%struct.S2, %struct.S2* @struct_s2, i32 0), align 1
|
|
|
365 store %struct.S2 %0, %struct.S2* getelementptr inbounds (%struct.S2, %struct.S2* @struct_s2, i32 1), align 1
|
|
77
|
366 ret void
|
|
|
367 }
|
|
|
368
|
|
|
369 ;
|
|
|
370 ; Arrays are simply concatenations of the members. They are unaffected by
|
|
|
371 ; endianness
|
|
|
372 ;
|
|
|
373
|
|
|
374 @arr = common global [7 x i8] zeroinitializer, align 1
|
|
|
375
|
|
|
376 define void @pass_array_byval() nounwind {
|
|
|
377 entry:
|
|
|
378 ; ALL-LABEL: pass_array_byval:
|
|
|
379
|
|
|
380 ; MIPS32-EL: lw $[[SPTR:[0-9]+]], %got(arr)(
|
|
|
381 ; MIPS32-EL-DAG: lwl $[[R1:4]], 3($[[PTR]])
|
|
|
382 ; MIPS32-EL-DAG: lwr $[[R1]], 0($[[PTR]])
|
|
|
383 ; MIPS32-EL-DAG: lbu $[[R2:[0-9]+]], 4($[[PTR]])
|
|
|
384 ; MIPS32-EL-DAG: lbu $[[R3:[0-9]+]], 5($[[PTR]])
|
|
|
385 ; MIPS32-EL-DAG: sll $[[T0:[0-9]+]], $[[R3]], 8
|
|
|
386 ; MIPS32-EL-DAG: or $[[T1:[0-9]+]], $[[T0]], $[[R2]]
|
|
|
387 ; MIPS32-EL-DAG: lbu $[[R4:[0-9]+]], 6($[[PTR]])
|
|
|
388 ; MIPS32-EL-DAG: sll $[[T2:[0-9]+]], $[[R4]], 16
|
|
|
389 ; MIPS32-EL-DAG: or $5, $[[T1]], $[[T2]]
|
|
|
390
|
|
|
391 ; MIPS32-EB: lw $[[SPTR:[0-9]+]], %got(arr)(
|
|
|
392 ; MIPS32-EB-DAG: lwl $[[R1:4]], 0($[[PTR]])
|
|
|
393 ; MIPS32-EB-DAG: lwr $[[R1]], 3($[[PTR]])
|
|
|
394 ; MIPS32-EB-DAG: lbu $[[R2:[0-9]+]], 5($[[PTR]])
|
|
|
395 ; MIPS32-EB-DAG: lbu $[[R3:[0-9]+]], 4($[[PTR]])
|
|
|
396 ; MIPS32-EB-DAG: sll $[[T0:[0-9]+]], $[[R3]], 8
|
|
|
397 ; MIPS32-EB-DAG: or $[[T1:[0-9]+]], $[[T0]], $[[R2]]
|
|
|
398 ; MIPS32-EB-DAG: sll $[[T1]], $[[T1]], 16
|
|
|
399 ; MIPS32-EB-DAG: lbu $[[R4:[0-9]+]], 6($[[PTR]])
|
|
|
400 ; MIPS32-EB-DAG: sll $[[T2:[0-9]+]], $[[R4]], 8
|
|
|
401 ; MIPS32-EB-DAG: or $5, $[[T1]], $[[T2]]
|
|
|
402
|
|
|
403 ; MIPS32R6: lw $[[SPTR:[0-9]+]], %got(arr)(
|
|
|
404 ; MIPS32R6-DAG: lw $4, 0($[[PTR]])
|
|
|
405 ; MIPS32R6-EL-DAG: lhu $[[R2:[0-9]+]], 4($[[PTR]])
|
|
|
406 ; MIPS32R6-EL-DAG: lbu $[[R3:[0-9]+]], 6($[[PTR]])
|
|
|
407 ; MIPS32R6-EL-DAG: sll $[[T0:[0-9]+]], $[[R3]], 16
|
|
|
408 ; MIPS32R6-EL-DAG: or $5, $[[R2]], $[[T0]]
|
|
|
409
|
|
|
410 ; MIPS32R6-EB-DAG: lhu $[[R2:[0-9]+]], 4($[[PTR]])
|
|
|
411 ; MIPS32R6-EB-DAG: lbu $[[R3:[0-9]+]], 6($[[PTR]])
|
|
|
412 ; MIPS32R6-EB-DAG: sll $[[T0:[0-9]+]], $[[R2]], 16
|
|
|
413 ; MIPS32R6-EB-DAG: or $5, $[[T0]], $[[R3]]
|
|
|
414
|
|
|
415 ; MIPS64-EL: ld $[[SPTR:[0-9]+]], %got_disp(arr)(
|
|
|
416 ; MIPS64-EL-DAG: lwl $[[R1:[0-9]+]], 3($[[PTR]])
|
|
|
417 ; MIPS64-EL-DAG: lwr $[[R1]], 0($[[PTR]])
|
|
|
418
|
|
|
419 ; MIPS64-EB: ld $[[SPTR:[0-9]+]], %got_disp(arr)(
|
|
|
420 ; MIPS64-EB-DAG: lwl $[[R1:[0-9]+]], 0($[[PTR]])
|
|
|
421 ; MIPS64-EB-DAG: lwr $[[R1]], 3($[[PTR]])
|
|
|
422 ; MIPS64-EB-DAG: dsll $[[R1]], $[[R1]], 32
|
|
|
423 ; MIPS64-EB-DAG: lbu $[[R2:[0-9]+]], 5($[[PTR]])
|
|
|
424 ; MIPS64-EB-DAG: lbu $[[R3:[0-9]+]], 4($[[PTR]])
|
|
|
425 ; MIPS64-EB-DAG: dsll $[[T0:[0-9]+]], $[[R3]], 8
|
|
|
426 ; MIPS64-EB-DAG: or $[[T1:[0-9]+]], $[[T0]], $[[R2]]
|
|
|
427 ; MIPS64-EB-DAG: dsll $[[T1]], $[[T1]], 16
|
|
|
428 ; MIPS64-EB-DAG: or $[[T3:[0-9]+]], $[[R1]], $[[T1]]
|
|
|
429 ; MIPS64-EB-DAG: lbu $[[R4:[0-9]+]], 6($[[PTR]])
|
|
|
430 ; MIPS64-EB-DAG: dsll $[[T4:[0-9]+]], $[[R4]], 8
|
|
|
431 ; MIPS64-EB-DAG: or $4, $[[T3]], $[[T4]]
|
|
|
432
|
|
|
433 ; MIPS64R6: ld $[[SPTR:[0-9]+]], %got_disp(arr)(
|
|
|
434
|
|
|
435 tail call void @extern_func([7 x i8]* byval @arr) nounwind
|
|
|
436 ret void
|
|
|
437 }
|
|
|
438
|
|
|
439 declare void @extern_func([7 x i8]* byval)
|
