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annotate test/CodeGen/Mips/msa/2rf_tq.ll @ 117:facf19d07cd9

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check EHStack on EmitCall (CbC goto)
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Wed, 24 Aug 2016 20:10:41 +0900
parents afa8332a0e37
children
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1 ; Test the MSA floating-point to fixed-point conversion intrinsics that are
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2 ; encoded with the 2RF instruction format.
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3
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4 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
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5 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
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7 @llvm_mips_ftq_h_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
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8 @llvm_mips_ftq_h_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
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9 @llvm_mips_ftq_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
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10
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11 define void @llvm_mips_ftq_h_test() nounwind {
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12 entry:
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13 %0 = load <4 x float>, <4 x float>* @llvm_mips_ftq_h_ARG1
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14 %1 = load <4 x float>, <4 x float>* @llvm_mips_ftq_h_ARG2
0
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15 %2 = tail call <8 x i16> @llvm.mips.ftq.h(<4 x float> %0, <4 x float> %1)
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16 store <8 x i16> %2, <8 x i16>* @llvm_mips_ftq_h_RES
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17 ret void
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18 }
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20 declare <8 x i16> @llvm.mips.ftq.h(<4 x float>, <4 x float>) nounwind
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21
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22 ; CHECK: llvm_mips_ftq_h_test:
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23 ; CHECK: ld.w
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24 ; CHECK: ld.w
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25 ; CHECK: ftq.h
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26 ; CHECK: st.h
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27 ; CHECK: .size llvm_mips_ftq_h_test
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28 ;
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29 @llvm_mips_ftq_w_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
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30 @llvm_mips_ftq_w_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
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31 @llvm_mips_ftq_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
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32
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33 define void @llvm_mips_ftq_w_test() nounwind {
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34 entry:
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35 %0 = load <2 x double>, <2 x double>* @llvm_mips_ftq_w_ARG1
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36 %1 = load <2 x double>, <2 x double>* @llvm_mips_ftq_w_ARG2
0
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37 %2 = tail call <4 x i32> @llvm.mips.ftq.w(<2 x double> %0, <2 x double> %1)
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38 store <4 x i32> %2, <4 x i32>* @llvm_mips_ftq_w_RES
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39 ret void
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40 }
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42 declare <4 x i32> @llvm.mips.ftq.w(<2 x double>, <2 x double>) nounwind
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43
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44 ; CHECK: llvm_mips_ftq_w_test:
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45 ; CHECK: ld.d
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46 ; CHECK: ld.d
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47 ; CHECK: ftq.w
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48 ; CHECK: st.w
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49 ; CHECK: .size llvm_mips_ftq_w_test
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50 ;