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annotate test/CodeGen/Mips/msa/3rf_q.ll @ 117:facf19d07cd9

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check EHStack on EmitCall (CbC goto)
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Wed, 24 Aug 2016 20:10:41 +0900
parents afa8332a0e37
children
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1 ; Test the MSA fixed-point intrinsics that are encoded with the 3RF instruction
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2 ; format.
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3
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4 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
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5 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
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6
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7 @llvm_mips_mul_q_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
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8 @llvm_mips_mul_q_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
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9 @llvm_mips_mul_q_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
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10
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11 define void @llvm_mips_mul_q_h_test() nounwind {
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12 entry:
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13 %0 = load <8 x i16>, <8 x i16>* @llvm_mips_mul_q_h_ARG1
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14 %1 = load <8 x i16>, <8 x i16>* @llvm_mips_mul_q_h_ARG2
0
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15 %2 = tail call <8 x i16> @llvm.mips.mul.q.h(<8 x i16> %0, <8 x i16> %1)
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16 store <8 x i16> %2, <8 x i16>* @llvm_mips_mul_q_h_RES
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17 ret void
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18 }
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19
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20 declare <8 x i16> @llvm.mips.mul.q.h(<8 x i16>, <8 x i16>) nounwind
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21
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22 ; CHECK: llvm_mips_mul_q_h_test:
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23 ; CHECK: ld.h
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24 ; CHECK: ld.h
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25 ; CHECK: mul_q.h
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26 ; CHECK: st.h
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27 ; CHECK: .size llvm_mips_mul_q_h_test
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28 ;
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29 @llvm_mips_mul_q_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
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30 @llvm_mips_mul_q_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
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31 @llvm_mips_mul_q_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
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32
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33 define void @llvm_mips_mul_q_w_test() nounwind {
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34 entry:
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35 %0 = load <4 x i32>, <4 x i32>* @llvm_mips_mul_q_w_ARG1
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36 %1 = load <4 x i32>, <4 x i32>* @llvm_mips_mul_q_w_ARG2
0
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37 %2 = tail call <4 x i32> @llvm.mips.mul.q.w(<4 x i32> %0, <4 x i32> %1)
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38 store <4 x i32> %2, <4 x i32>* @llvm_mips_mul_q_w_RES
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39 ret void
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40 }
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41
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42 declare <4 x i32> @llvm.mips.mul.q.w(<4 x i32>, <4 x i32>) nounwind
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43
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44 ; CHECK: llvm_mips_mul_q_w_test:
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45 ; CHECK: ld.w
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46 ; CHECK: ld.w
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47 ; CHECK: mul_q.w
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48 ; CHECK: st.w
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49 ; CHECK: .size llvm_mips_mul_q_w_test
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50 ;
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51 @llvm_mips_mulr_q_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
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52 @llvm_mips_mulr_q_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
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53 @llvm_mips_mulr_q_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
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54
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55 define void @llvm_mips_mulr_q_h_test() nounwind {
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56 entry:
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57 %0 = load <8 x i16>, <8 x i16>* @llvm_mips_mulr_q_h_ARG1
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58 %1 = load <8 x i16>, <8 x i16>* @llvm_mips_mulr_q_h_ARG2
0
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59 %2 = tail call <8 x i16> @llvm.mips.mulr.q.h(<8 x i16> %0, <8 x i16> %1)
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60 store <8 x i16> %2, <8 x i16>* @llvm_mips_mulr_q_h_RES
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61 ret void
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62 }
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63
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64 declare <8 x i16> @llvm.mips.mulr.q.h(<8 x i16>, <8 x i16>) nounwind
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65
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66 ; CHECK: llvm_mips_mulr_q_h_test:
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67 ; CHECK: ld.h
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68 ; CHECK: ld.h
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69 ; CHECK: mulr_q.h
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70 ; CHECK: st.h
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71 ; CHECK: .size llvm_mips_mulr_q_h_test
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72 ;
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73 @llvm_mips_mulr_q_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
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74 @llvm_mips_mulr_q_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
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75 @llvm_mips_mulr_q_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
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76
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77 define void @llvm_mips_mulr_q_w_test() nounwind {
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78 entry:
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79 %0 = load <4 x i32>, <4 x i32>* @llvm_mips_mulr_q_w_ARG1
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80 %1 = load <4 x i32>, <4 x i32>* @llvm_mips_mulr_q_w_ARG2
0
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81 %2 = tail call <4 x i32> @llvm.mips.mulr.q.w(<4 x i32> %0, <4 x i32> %1)
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82 store <4 x i32> %2, <4 x i32>* @llvm_mips_mulr_q_w_RES
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83 ret void
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84 }
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85
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86 declare <4 x i32> @llvm.mips.mulr.q.w(<4 x i32>, <4 x i32>) nounwind
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87
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88 ; CHECK: llvm_mips_mulr_q_w_test:
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89 ; CHECK: ld.w
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90 ; CHECK: ld.w
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91 ; CHECK: mulr_q.w
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92 ; CHECK: st.w
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93 ; CHECK: .size llvm_mips_mulr_q_w_test
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94 ;