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annotate test/CodeGen/Mips/seleqk.ll @ 117:facf19d07cd9

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author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Wed, 24 Aug 2016 20:10:41 +0900
parents 7d135dc70f03
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
100
7d135dc70f03 LLVM 3.9
Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
diff changeset
1 ; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16
0
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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2
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3 @t = global i32 10, align 4
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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4 @f = global i32 199, align 4
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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5 @a = global i32 1, align 4
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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6 @b = global i32 1000, align 4
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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7 @z1 = common global i32 0, align 4
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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8 @z2 = common global i32 0, align 4
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9 @z3 = common global i32 0, align 4
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10 @z4 = common global i32 0, align 4
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parents:
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11 @.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1
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12
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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13 define void @calc_seleqk() nounwind "target-cpu"="mips16" "target-features"="+mips16,+o32" {
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parents:
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14 entry:
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afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
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15 %0 = load i32, i32* @a, align 4
0
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parents:
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16 %cmp = icmp eq i32 %0, 1
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17 br i1 %cmp, label %cond.true, label %cond.false
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18
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19 cond.true: ; preds = %entry
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parents: 0
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20 %1 = load i32, i32* @t, align 4
0
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21 br label %cond.end
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22
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23 cond.false: ; preds = %entry
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parents: 0
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24 %2 = load i32, i32* @f, align 4
0
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25 br label %cond.end
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26
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27 cond.end: ; preds = %cond.false, %cond.true
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28 %cond = phi i32 [ %1, %cond.true ], [ %2, %cond.false ]
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parents:
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29 store i32 %cond, i32* @z1, align 4
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parents: 0
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30 %3 = load i32, i32* @a, align 4
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31 %cmp1 = icmp eq i32 %3, 1000
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32 br i1 %cmp1, label %cond.true2, label %cond.false3
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33
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34 cond.true2: ; preds = %cond.end
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parents: 0
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35 %4 = load i32, i32* @f, align 4
0
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36 br label %cond.end4
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37
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38 cond.false3: ; preds = %cond.end
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parents: 0
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39 %5 = load i32, i32* @t, align 4
0
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40 br label %cond.end4
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41
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42 cond.end4: ; preds = %cond.false3, %cond.true2
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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43 %cond5 = phi i32 [ %4, %cond.true2 ], [ %5, %cond.false3 ]
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parents:
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44 store i32 %cond5, i32* @z2, align 4
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parents: 0
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45 %6 = load i32, i32* @b, align 4
0
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46 %cmp6 = icmp eq i32 %6, 3
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parents:
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47 br i1 %cmp6, label %cond.true7, label %cond.false8
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48
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49 cond.true7: ; preds = %cond.end4
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parents: 0
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50 %7 = load i32, i32* @f, align 4
0
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51 br label %cond.end9
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52
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53 cond.false8: ; preds = %cond.end4
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parents: 0
diff changeset
54 %8 = load i32, i32* @t, align 4
0
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parents:
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55 br label %cond.end9
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56
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57 cond.end9: ; preds = %cond.false8, %cond.true7
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parents:
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58 %cond10 = phi i32 [ %7, %cond.true7 ], [ %8, %cond.false8 ]
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parents:
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59 store i32 %cond10, i32* @z3, align 4
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parents: 0
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60 %9 = load i32, i32* @b, align 4
0
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61 %cmp11 = icmp eq i32 %9, 1000
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parents:
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62 br i1 %cmp11, label %cond.true12, label %cond.false13
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parents:
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63
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parents:
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64 cond.true12: ; preds = %cond.end9
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parents: 0
diff changeset
65 %10 = load i32, i32* @t, align 4
0
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66 br label %cond.end14
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67
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68 cond.false13: ; preds = %cond.end9
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parents: 0
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69 %11 = load i32, i32* @f, align 4
0
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70 br label %cond.end14
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71
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72 cond.end14: ; preds = %cond.false13, %cond.true12
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73 %cond15 = phi i32 [ %10, %cond.true12 ], [ %11, %cond.false13 ]
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parents:
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74 store i32 %cond15, i32* @z4, align 4
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75 ret void
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76 }
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77
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78 attributes #0 = { nounwind "target-cpu"="mips16" "target-features"="+mips16,+o32" }
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79 attributes #1 = { "target-cpu"="mips16" "target-features"="+mips16,+o32" }
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80
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81 ; 16: cmpi ${{[0-9]+}}, 1 # 16 bit inst
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parents:
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82 ; 16: btnez $BB{{[0-9]+}}_{{[0-9]}}
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83
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84 ; 16: cmpi ${{[0-9]+}}, 1000
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85 ; 16: btnez $BB{{[0-9]+}}_{{[0-9]}}
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86
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87 ; 16: cmpi ${{[0-9]+}}, 3 # 16 bit inst
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parents:
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88 ; 16: btnez $BB{{[0-9]+}}_{{[0-9]}}
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89
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90 ; 16: cmpi ${{[0-9]+}}, 1000
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parents:
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91 ; 16: btnez $BB{{[0-9]+}}_{{[0-9]}}