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annotate test/CodeGen/Mips/selltk.ll @ 117:facf19d07cd9

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author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Wed, 24 Aug 2016 20:10:41 +0900
parents 7d135dc70f03
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
100
7d135dc70f03 LLVM 3.9
Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
diff changeset
1 ; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16
0
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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2
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parents:
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3 @t = global i32 10, align 4
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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4 @f = global i32 199, align 4
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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5 @a = global i32 2, align 4
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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6 @b = global i32 1000, align 4
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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7 @c = global i32 2, align 4
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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8 @z1 = common global i32 0, align 4
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parents:
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9 @z2 = common global i32 0, align 4
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parents:
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10 @z3 = common global i32 0, align 4
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parents:
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11 @z4 = common global i32 0, align 4
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parents:
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12 @.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1
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parents:
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13
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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14 define void @calc_selltk() nounwind "target-cpu"="mips16" "target-features"="+mips16,+o32" {
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parents:
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15 entry:
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parents: 0
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16 %0 = load i32, i32* @a, align 4
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parents:
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17 %cmp = icmp slt i32 %0, 1000
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parents:
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18 br i1 %cmp, label %cond.true, label %cond.false
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19
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20 cond.true: ; preds = %entry
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parents: 0
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21 %1 = load i32, i32* @t, align 4
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22 br label %cond.end
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23
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24 cond.false: ; preds = %entry
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parents: 0
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25 %2 = load i32, i32* @f, align 4
0
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26 br label %cond.end
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27
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28 cond.end: ; preds = %cond.false, %cond.true
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29 %cond = phi i32 [ %1, %cond.true ], [ %2, %cond.false ]
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parents:
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30 store i32 %cond, i32* @z1, align 4
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parents: 0
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31 %3 = load i32, i32* @b, align 4
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32 %cmp1 = icmp slt i32 %3, 2
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33 br i1 %cmp1, label %cond.true2, label %cond.false3
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34
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35 cond.true2: ; preds = %cond.end
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parents: 0
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36 %4 = load i32, i32* @f, align 4
0
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37 br label %cond.end4
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38
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39 cond.false3: ; preds = %cond.end
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parents: 0
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40 %5 = load i32, i32* @t, align 4
0
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41 br label %cond.end4
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42
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43 cond.end4: ; preds = %cond.false3, %cond.true2
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parents:
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44 %cond5 = phi i32 [ %4, %cond.true2 ], [ %5, %cond.false3 ]
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parents:
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45 store i32 %cond5, i32* @z2, align 4
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parents: 0
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46 %6 = load i32, i32* @c, align 4
0
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parents:
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47 %cmp6 = icmp sgt i32 %6, 2
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parents:
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48 br i1 %cmp6, label %cond.true7, label %cond.false8
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parents:
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49
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50 cond.true7: ; preds = %cond.end4
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parents: 0
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51 %7 = load i32, i32* @f, align 4
0
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parents:
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52 br label %cond.end9
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53
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54 cond.false8: ; preds = %cond.end4
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parents: 0
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55 %8 = load i32, i32* @t, align 4
0
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56 br label %cond.end9
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57
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58 cond.end9: ; preds = %cond.false8, %cond.true7
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parents:
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59 %cond10 = phi i32 [ %7, %cond.true7 ], [ %8, %cond.false8 ]
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parents:
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60 store i32 %cond10, i32* @z3, align 4
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parents: 0
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61 %9 = load i32, i32* @a, align 4
0
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parents:
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62 %cmp11 = icmp sgt i32 %9, 2
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parents:
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63 br i1 %cmp11, label %cond.true12, label %cond.false13
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parents:
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64
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parents:
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65 cond.true12: ; preds = %cond.end9
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parents: 0
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66 %10 = load i32, i32* @f, align 4
0
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parents:
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67 br label %cond.end14
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68
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69 cond.false13: ; preds = %cond.end9
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parents: 0
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70 %11 = load i32, i32* @t, align 4
0
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71 br label %cond.end14
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72
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73 cond.end14: ; preds = %cond.false13, %cond.true12
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parents:
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74 %cond15 = phi i32 [ %10, %cond.true12 ], [ %11, %cond.false13 ]
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parents:
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75 store i32 %cond15, i32* @z4, align 4
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76 ret void
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77 }
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78
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79 attributes #0 = { nounwind "target-cpu"="mips16" "target-features"="+mips16,+o32" }
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80 attributes #1 = { "target-cpu"="mips16" "target-features"="+mips16,+o32" }
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81
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82 ; 16: slt ${{[0-9]+}}, ${{[0-9]+}}
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parents:
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83 ; 16: btnez $BB{{[0-9]+}}_{{[0-9]}}
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84
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85 ; 16: slt ${{[0-9]+}}, ${{[0-9]+}}
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86 ; 16: btnez $BB{{[0-9]+}}_{{[0-9]}}
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87
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88 ; 16: slti ${{[0-9]+}}, 3 # 16 bit inst
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parents:
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89 ; 16: btnez $BB{{[0-9]+}}_{{[0-9]}}
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90
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91 ; 16: slti ${{[0-9]+}}, 3 # 16 bit inst
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parents:
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92 ; 16: btnez $BB{{[0-9]+}}_{{[0-9]}}
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parents:
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93