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annotate test/CodeGen/Mips/unalignedload.ll @ 117:facf19d07cd9

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author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Wed, 24 Aug 2016 20:10:41 +0900
parents afa8332a0e37
children 1172e4bd9c6f
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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1 ; RUN: llc < %s -march=mipsel -mcpu=mips32 | FileCheck %s -check-prefix=ALL -check-prefix=ALL-EL -check-prefix=MIPS32-EL
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2 ; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s -check-prefix=ALL -check-prefix=ALL-EB -check-prefix=MIPS32-EB
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3 ; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=ALL -check-prefix=ALL-EL -check-prefix=MIPS32-EL
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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4 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s -check-prefix=ALL -check-prefix=ALL-EB -check-prefix=MIPS32-EB
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5 ; RUN: llc < %s -march=mipsel -mcpu=mips32r6 | FileCheck %s -check-prefix=ALL -check-prefix=ALL-EL -check-prefix=MIPS32R6-EL
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6 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s -check-prefix=ALL -check-prefix=ALL-EB -check-prefix=MIPS32R6-EB
0
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7 %struct.S2 = type { %struct.S1, %struct.S1 }
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8 %struct.S1 = type { i8, i8 }
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9 %struct.S4 = type { [7 x i8] }
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10
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11 @s2 = common global %struct.S2 zeroinitializer, align 1
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12 @s4 = common global %struct.S4 zeroinitializer, align 1
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13
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14 define void @bar1() nounwind {
0
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15 entry:
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16 ; ALL-LABEL: bar1:
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17
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18 ; ALL-DAG: lw $[[R0:[0-9]+]], %got(s2)(
0
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19
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20 ; MIPS32-EL-DAG: lbu $[[PART1:[0-9]+]], 2($[[R0]])
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21 ; MIPS32-EL-DAG: lbu $[[PART2:[0-9]+]], 3($[[R0]])
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22 ; MIPS32-EL-DAG: sll $[[T0:[0-9]+]], $[[PART2]], 8
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23 ; MIPS32-EL-DAG: or $4, $[[T0]], $[[PART1]]
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24
54457678186b LLVM 3.6
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25 ; MIPS32-EB-DAG: lbu $[[PART1:[0-9]+]], 2($[[R0]])
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26 ; MIPS32-EB-DAG: lbu $[[PART2:[0-9]+]], 3($[[R0]])
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27 ; MIPS32-EB-DAG: sll $[[T0:[0-9]+]], $[[PART1]], 8
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28 ; MIPS32-EB-DAG: or $[[T1:[0-9]+]], $[[T0]], $[[PART2]]
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29 ; MIPS32-EB-DAG: sll $4, $[[T1]], 16
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30
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31 ; MIPS32R6-DAG: lhu $[[PART1:[0-9]+]], 2($[[R0]])
0
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afa8332a0e37 LLVM 3.8
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33 tail call void @foo2(%struct.S1* byval getelementptr inbounds (%struct.S2, %struct.S2* @s2, i32 0, i32 1)) nounwind
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34 ret void
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35 }
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36
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37 define void @bar2() nounwind {
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38 entry:
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39 ; ALL-LABEL: bar2:
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40
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41 ; ALL-DAG: lw $[[R2:[0-9]+]], %got(s4)(
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42
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43 ; MIPS32-EL-DAG: lwl $[[R1:4]], 3($[[R2]])
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44 ; MIPS32-EL-DAG: lwr $[[R1]], 0($[[R2]])
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45 ; MIPS32-EL-DAG: lbu $[[T0:[0-9]+]], 4($[[R2]])
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46 ; MIPS32-EL-DAG: lbu $[[T1:[0-9]+]], 5($[[R2]])
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47 ; MIPS32-EL-DAG: lbu $[[T2:[0-9]+]], 6($[[R2]])
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48 ; MIPS32-EL-DAG: sll $[[T3:[0-9]+]], $[[T1]], 8
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49 ; MIPS32-EL-DAG: or $[[T4:[0-9]+]], $[[T3]], $[[T0]]
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50 ; MIPS32-EL-DAG: sll $[[T5:[0-9]+]], $[[T2]], 16
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51 ; MIPS32-EL-DAG: or $5, $[[T4]], $[[T5]]
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52
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53 ; MIPS32-EB-DAG: lwl $[[R1:4]], 0($[[R2]])
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54 ; MIPS32-EB-DAG: lwr $[[R1]], 3($[[R2]])
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55 ; MIPS32-EB-DAG: lbu $[[T0:[0-9]+]], 4($[[R2]])
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56 ; MIPS32-EB-DAG: lbu $[[T1:[0-9]+]], 5($[[R2]])
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57 ; MIPS32-EB-DAG: lbu $[[T2:[0-9]+]], 6($[[R2]])
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58 ; MIPS32-EB-DAG: sll $[[T3:[0-9]+]], $[[T0]], 8
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parents: 0
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59 ; MIPS32-EB-DAG: or $[[T4:[0-9]+]], $[[T3]], $[[T1]]
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60 ; MIPS32-EB-DAG: sll $[[T5:[0-9]+]], $[[T4]], 16
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61 ; MIPS32-EB-DAG: sll $[[T6:[0-9]+]], $[[T2]], 8
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parents: 0
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62 ; MIPS32-EB-DAG: or $5, $[[T5]], $[[T6]]
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63
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64 ; FIXME: We should be able to do better than this using lhu
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65 ; MIPS32R6-EL-DAG: lw $4, 0($[[R2]])
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66 ; MIPS32R6-EL-DAG: lhu $[[T0:[0-9]+]], 4($[[R2]])
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67 ; MIPS32R6-EL-DAG: lbu $[[T1:[0-9]+]], 6($[[R2]])
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68 ; MIPS32R6-EL-DAG: sll $[[T2:[0-9]+]], $[[T1]], 16
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69 ; MIPS32R6-EL-DAG: or $5, $[[T0]], $[[T2]]
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70
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71 ; FIXME: We should be able to do better than this using lhu
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72 ; MIPS32R6-EB-DAG: lw $4, 0($[[R2]])
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73 ; MIPS32R6-EB-DAG: lhu $[[T0:[0-9]+]], 4($[[R2]])
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74 ; MIPS32R6-EB-DAG: lbu $[[T1:[0-9]+]], 6($[[R2]])
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75 ; MIPS32R6-EB-DAG: sll $[[T2:[0-9]+]], $[[T0]], 16
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76 ; MIPS32R6-EB-DAG: sll $[[T3:[0-9]+]], $[[T1]], 8
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77 ; MIPS32R6-EB-DAG: or $5, $[[T2]], $[[T3]]
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78
0
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79 tail call void @foo4(%struct.S4* byval @s4) nounwind
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80 ret void
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81 }
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83 declare void @foo2(%struct.S1* byval)
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84
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85 declare void @foo4(%struct.S4* byval)