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1 //===- ARCInstrInfo.h - ARC Instruction Information -------------*- C++ -*-===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 // This file contains the ARC implementation of the TargetInstrInfo class.
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11 //
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12 //===----------------------------------------------------------------------===//
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13
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14 #ifndef LLVM_LIB_TARGET_ARC_ARCINSTRINFO_H
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15 #define LLVM_LIB_TARGET_ARC_ARCINSTRINFO_H
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16
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17 #include "ARCRegisterInfo.h"
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18 #include "llvm/Target/TargetInstrInfo.h"
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19
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20 #define GET_INSTRINFO_HEADER
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21 #include "ARCGenInstrInfo.inc"
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22
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23 namespace llvm {
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24
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25 class ARCSubtarget;
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26
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27 class ARCInstrInfo : public ARCGenInstrInfo {
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28 const ARCRegisterInfo RI;
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29 virtual void anchor();
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30
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31 public:
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32 ARCInstrInfo();
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33
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34 const ARCRegisterInfo &getRegisterInfo() const { return RI; }
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35
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36 /// If the specified machine instruction is a direct
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37 /// load from a stack slot, return the virtual or physical register number of
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38 /// the destination along with the FrameIndex of the loaded stack slot. If
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39 /// not, return 0. This predicate must return 0 if the instruction has
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40 /// any side effects other than loading from the stack slot.
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41 unsigned isLoadFromStackSlot(const MachineInstr &MI,
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42 int &FrameIndex) const override;
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43
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44 /// If the specified machine instruction is a direct
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45 /// store to a stack slot, return the virtual or physical register number of
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46 /// the source reg along with the FrameIndex of the loaded stack slot. If
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47 /// not, return 0. This predicate must return 0 if the instruction has
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48 /// any side effects other than storing to the stack slot.
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49 unsigned isStoreToStackSlot(const MachineInstr &MI,
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50 int &FrameIndex) const override;
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51
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52 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
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53
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54 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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55 MachineBasicBlock *&FBB,
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56 SmallVectorImpl<MachineOperand> &Cond,
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57 bool AllowModify) const override;
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58
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59 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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60 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
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61 const DebugLoc &dl,
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62 int *BytesAdded = nullptr) const override;
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63
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64 unsigned removeBranch(MachineBasicBlock &MBB,
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65 int *BytesRemoved = nullptr) const override;
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66
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67 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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68 const DebugLoc &dl, unsigned DestReg, unsigned SrcReg,
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69 bool KillSrc) const override;
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70
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71 void storeRegToStackSlot(MachineBasicBlock &MBB,
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72 MachineBasicBlock::iterator MI, unsigned SrcReg,
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73 bool isKill, int FrameIndex,
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74 const TargetRegisterClass *RC,
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75 const TargetRegisterInfo *TRI) const override;
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76
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77 void loadRegFromStackSlot(MachineBasicBlock &MBB,
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78 MachineBasicBlock::iterator MI, unsigned DestReg,
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79 int FrameIndex, const TargetRegisterClass *RC,
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80 const TargetRegisterInfo *TRI) const override;
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81
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82 bool
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83 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
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84
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85 // Emit code before MBBI to load immediate value into physical register Reg.
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86 // Returns an iterator to the new instruction.
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87 MachineBasicBlock::iterator loadImmediate(MachineBasicBlock &MBB,
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88 MachineBasicBlock::iterator MI,
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89 unsigned Reg, uint64_t Value) const;
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90 };
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91
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92 } // end namespace llvm
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93
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94 #endif // LLVM_LIB_TARGET_ARC_ARCINSTRINFO_H
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