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1 //===------------- PPCExpandISEL.cpp - Expand ISEL instruction ------------===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 // A pass that expands the ISEL instruction into an if-then-else sequence.
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11 // This pass must be run post-RA since all operands must be physical registers.
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12 //
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13 //===----------------------------------------------------------------------===//
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14
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15 #include "PPC.h"
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16 #include "PPCInstrInfo.h"
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17 #include "PPCSubtarget.h"
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18 #include "llvm/ADT/DenseMap.h"
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19 #include "llvm/ADT/Statistic.h"
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20 #include "llvm/CodeGen/LivePhysRegs.h"
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21 #include "llvm/CodeGen/MachineFunctionPass.h"
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22 #include "llvm/CodeGen/MachineInstrBuilder.h"
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23 #include "llvm/CodeGen/MachineRegisterInfo.h"
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24 #include "llvm/Support/CommandLine.h"
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25 #include "llvm/Support/Debug.h"
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26 #include "llvm/Support/raw_ostream.h"
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27
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28 using namespace llvm;
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29
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30 #define DEBUG_TYPE "ppc-expand-isel"
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31
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32 STATISTIC(NumExpanded, "Number of ISEL instructions expanded");
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33 STATISTIC(NumRemoved, "Number of ISEL instructions removed");
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34 STATISTIC(NumFolded, "Number of ISEL instructions folded");
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35
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36 // If -ppc-gen-isel=false is set, we will disable generating the ISEL
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37 // instruction on all PPC targets. Otherwise, if the user set option
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38 // -misel or the platform supports ISEL by default, still generate the
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39 // ISEL instruction, else expand it.
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40 static cl::opt<bool>
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41 GenerateISEL("ppc-gen-isel",
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42 cl::desc("Enable generating the ISEL instruction."),
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43 cl::init(true), cl::Hidden);
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44
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45 namespace {
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46 class PPCExpandISEL : public MachineFunctionPass {
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47 DebugLoc dl;
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48 MachineFunction *MF;
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49 const TargetInstrInfo *TII;
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50 bool IsTrueBlockRequired;
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51 bool IsFalseBlockRequired;
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52 MachineBasicBlock *TrueBlock;
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53 MachineBasicBlock *FalseBlock;
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54 MachineBasicBlock *NewSuccessor;
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55 MachineBasicBlock::iterator TrueBlockI;
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56 MachineBasicBlock::iterator FalseBlockI;
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57
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58 typedef SmallVector<MachineInstr *, 4> BlockISELList;
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59 typedef SmallDenseMap<int, BlockISELList> ISELInstructionList;
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60
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61 // A map of MBB numbers to their lists of contained ISEL instructions.
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62 ISELInstructionList ISELInstructions;
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63
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64 /// Initialize the object.
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65 void initialize(MachineFunction &MFParam);
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66
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67 void handleSpecialCases(BlockISELList &BIL, MachineBasicBlock *MBB);
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68 void reorganizeBlockLayout(BlockISELList &BIL, MachineBasicBlock *MBB);
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69 void populateBlocks(BlockISELList &BIL);
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70 void expandMergeableISELs(BlockISELList &BIL);
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71 void expandAndMergeISELs();
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72
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73 bool canMerge(MachineInstr *PrevPushedMI, MachineInstr *MI);
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74
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75 /// Is this instruction an ISEL or ISEL8?
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76 static bool isISEL(const MachineInstr &MI) {
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77 return (MI.getOpcode() == PPC::ISEL || MI.getOpcode() == PPC::ISEL8);
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78 }
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79
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80 /// Is this instruction an ISEL8?
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81 static bool isISEL8(const MachineInstr &MI) {
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82 return (MI.getOpcode() == PPC::ISEL8);
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83 }
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84
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85 /// Are the two operands using the same register?
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86 bool useSameRegister(const MachineOperand &Op1, const MachineOperand &Op2) {
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87 return (Op1.getReg() == Op2.getReg());
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88 }
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89
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90 ///
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91 /// Collect all ISEL instructions from the current function.
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92 ///
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93 /// Walk the current function and collect all the ISEL instructions that are
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94 /// found. The instructions are placed in the ISELInstructions vector.
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95 ///
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96 /// \return true if any ISEL instructions were found, false otherwise
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97 ///
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98 bool collectISELInstructions();
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99
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100 public:
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101 static char ID;
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102 PPCExpandISEL() : MachineFunctionPass(ID) {
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103 initializePPCExpandISELPass(*PassRegistry::getPassRegistry());
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104 }
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105
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106 ///
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107 /// Determine whether to generate the ISEL instruction or expand it.
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108 ///
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109 /// Expand ISEL instruction into if-then-else sequence when one of
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110 /// the following two conditions hold:
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111 /// (1) -ppc-gen-isel=false
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112 /// (2) hasISEL() return false
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113 /// Otherwise, still generate ISEL instruction.
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114 /// The -ppc-gen-isel option is set to true by default. Which means the ISEL
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115 /// instruction is still generated by default on targets that support them.
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116 ///
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117 /// \return true if ISEL should be expanded into if-then-else code sequence;
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118 /// false if ISEL instruction should be generated, i.e. not expaned.
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119 ///
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120 static bool isExpandISELEnabled(const MachineFunction &MF);
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121
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122 #ifndef NDEBUG
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123 void DumpISELInstructions() const;
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124 #endif
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125
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126 bool runOnMachineFunction(MachineFunction &MF) override {
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127 if (!isExpandISELEnabled(MF))
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128 return false;
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129
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130 DEBUG(dbgs() << "Function: "; MF.dump(); dbgs() << "\n");
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131 initialize(MF);
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132
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133 if (!collectISELInstructions()) {
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134 DEBUG(dbgs() << "No ISEL instructions in this function\n");
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135 return false;
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136 }
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137
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138 #ifndef NDEBUG
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139 DumpISELInstructions();
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140 #endif
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141
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142 expandAndMergeISELs();
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143
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144 return true;
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145 }
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146 };
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147 } // end anonymous namespace
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148
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149 void PPCExpandISEL::initialize(MachineFunction &MFParam) {
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150 MF = &MFParam;
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151 TII = MF->getSubtarget().getInstrInfo();
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152 ISELInstructions.clear();
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153 }
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154
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155 bool PPCExpandISEL::isExpandISELEnabled(const MachineFunction &MF) {
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156 return !GenerateISEL || !MF.getSubtarget<PPCSubtarget>().hasISEL();
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157 }
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158
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159 bool PPCExpandISEL::collectISELInstructions() {
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160 for (MachineBasicBlock &MBB : *MF) {
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161 BlockISELList thisBlockISELs;
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162 for (MachineInstr &MI : MBB)
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163 if (isISEL(MI))
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164 thisBlockISELs.push_back(&MI);
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165 if (!thisBlockISELs.empty())
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166 ISELInstructions.insert(std::make_pair(MBB.getNumber(), thisBlockISELs));
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167 }
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168 return !ISELInstructions.empty();
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169 }
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170
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171 #ifndef NDEBUG
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172 void PPCExpandISEL::DumpISELInstructions() const {
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173 for (const auto &I : ISELInstructions) {
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174 DEBUG(dbgs() << "BB#" << I.first << ":\n");
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175 for (const auto &VI : I.second)
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176 DEBUG(dbgs() << " "; VI->print(dbgs()));
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177 }
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178 }
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179 #endif
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180
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181 /// Contiguous ISELs that have the same condition can be merged.
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182 bool PPCExpandISEL::canMerge(MachineInstr *PrevPushedMI, MachineInstr *MI) {
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183 // Same Condition Register?
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184 if (!useSameRegister(PrevPushedMI->getOperand(3), MI->getOperand(3)))
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185 return false;
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186
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187 MachineBasicBlock::iterator PrevPushedMBBI = *PrevPushedMI;
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188 MachineBasicBlock::iterator MBBI = *MI;
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189 return (std::prev(MBBI) == PrevPushedMBBI); // Contiguous ISELs?
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190 }
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191
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192 void PPCExpandISEL::expandAndMergeISELs() {
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193 for (auto &BlockList : ISELInstructions) {
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194 DEBUG(dbgs() << "Expanding ISEL instructions in BB#" << BlockList.first
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195 << "\n");
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196
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197 BlockISELList &CurrentISELList = BlockList.second;
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198 auto I = CurrentISELList.begin();
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199 auto E = CurrentISELList.end();
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200
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201 while (I != E) {
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202 BlockISELList SubISELList;
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203
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204 SubISELList.push_back(*I++);
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205
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206 // Collect the ISELs that can be merged together.
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207 while (I != E && canMerge(SubISELList.back(), *I))
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208 SubISELList.push_back(*I++);
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209
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210 expandMergeableISELs(SubISELList);
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211 }
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212 }
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213 }
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214
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215 void PPCExpandISEL::handleSpecialCases(BlockISELList &BIL,
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216 MachineBasicBlock *MBB) {
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217 IsTrueBlockRequired = false;
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218 IsFalseBlockRequired = false;
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219
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220 auto MI = BIL.begin();
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221 while (MI != BIL.end()) {
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222 assert(isISEL(**MI) && "Expecting an ISEL instruction");
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223 DEBUG(dbgs() << "ISEL: " << **MI << "\n");
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224
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225 MachineOperand &Dest = (*MI)->getOperand(0);
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226 MachineOperand &TrueValue = (*MI)->getOperand(1);
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227 MachineOperand &FalseValue = (*MI)->getOperand(2);
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228
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229 // If at least one of the ISEL instructions satisfy the following
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230 // condition, we need the True Block:
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231 // The Dest Register and True Value Register are not the same
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232 // Similarly, if at least one of the ISEL instructions satisfy the
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233 // following condition, we need the False Block:
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234 // The Dest Register and False Value Register are not the same.
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235
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236 bool IsADDIInstRequired = !useSameRegister(Dest, TrueValue);
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237 bool IsORIInstRequired = !useSameRegister(Dest, FalseValue);
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238
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239 // Special case 1, all registers used by ISEL are the same one.
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240 if (!IsADDIInstRequired && !IsORIInstRequired) {
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241 DEBUG(dbgs() << "Remove redudant ISEL instruction.");
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242 NumRemoved++;
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243 (*MI)->eraseFromParent();
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244 // Setting MI to the erase result keeps the iterator valid and increased.
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245 MI = BIL.erase(MI);
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246 continue;
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247 }
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248
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249 // Special case 2, the two input registers used by ISEL are the same.
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250 // Note 1: We favor merging ISEL expansions over folding a single one. If
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251 // the passed list has multiple merge-able ISEL's, we won't fold any.
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252 // Note 2: There is no need to test for PPC::R0/PPC::X0 because PPC::ZERO/
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253 // PPC::ZERO8 will be used for the first operand if the value is meant to
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254 // be zero. In this case, the useSameRegister method will return false,
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255 // thereby preventing this ISEL from being folded.
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256
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257 if (useSameRegister(TrueValue, FalseValue) && (BIL.size() == 1)) {
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258 DEBUG(dbgs() << "Fold the ISEL instruction to an unconditonal copy.");
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259 NumFolded++;
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260 BuildMI(*MBB, (*MI), dl, TII->get(isISEL8(**MI) ? PPC::ADDI8 : PPC::ADDI))
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261 .add(Dest)
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262 .add(TrueValue)
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263 .add(MachineOperand::CreateImm(0));
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264 (*MI)->eraseFromParent();
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265 // Setting MI to the erase result keeps the iterator valid and increased.
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266 MI = BIL.erase(MI);
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267 continue;
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268 }
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269
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270 IsTrueBlockRequired |= IsADDIInstRequired;
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271 IsFalseBlockRequired |= IsORIInstRequired;
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272 MI++;
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273 }
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274 }
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275
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276 void PPCExpandISEL::reorganizeBlockLayout(BlockISELList &BIL,
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277 MachineBasicBlock *MBB) {
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278 if (BIL.empty())
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279 return;
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280
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281 assert((IsTrueBlockRequired || IsFalseBlockRequired) &&
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282 "Should have been handled by special cases earlier!");
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283
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284 MachineBasicBlock *Successor = nullptr;
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285 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
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286 MachineBasicBlock::iterator MBBI = (*BIL.back());
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287 NewSuccessor = (MBBI != MBB->getLastNonDebugInstr() || !MBB->canFallThrough())
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288 // Another BB is needed to move the instructions that
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289 // follow this ISEL. If the ISEL is the last instruction
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290 // in a block that can't fall through, we also need a block
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291 // to branch to.
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292 ? MF->CreateMachineBasicBlock(LLVM_BB)
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293 : nullptr;
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294
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295 MachineFunction::iterator It = MBB->getIterator();
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296 ++It; // Point to the successor block of MBB.
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297
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298 // If NewSuccessor is NULL then the last ISEL in this group is the last
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299 // non-debug instruction in this block. Find the fall-through successor
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300 // of this block to use when updating the CFG below.
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301 if (!NewSuccessor) {
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302 for (auto &Succ : MBB->successors()) {
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303 if (MBB->isLayoutSuccessor(Succ)) {
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304 Successor = Succ;
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305 break;
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306 }
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307 }
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308 } else
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309 Successor = NewSuccessor;
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310
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311 // The FalseBlock and TrueBlock are inserted after the MBB block but before
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312 // its successor.
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313 // Note this need to be done *after* the above setting the Successor code.
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314 if (IsFalseBlockRequired) {
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315 FalseBlock = MF->CreateMachineBasicBlock(LLVM_BB);
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316 MF->insert(It, FalseBlock);
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317 }
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318
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319 if (IsTrueBlockRequired) {
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320 TrueBlock = MF->CreateMachineBasicBlock(LLVM_BB);
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321 MF->insert(It, TrueBlock);
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322 }
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323
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324 if (NewSuccessor) {
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325 MF->insert(It, NewSuccessor);
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326
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327 // Transfer the rest of this block into the new successor block.
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328 NewSuccessor->splice(NewSuccessor->end(), MBB,
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329 std::next(MachineBasicBlock::iterator(BIL.back())),
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330 MBB->end());
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331 NewSuccessor->transferSuccessorsAndUpdatePHIs(MBB);
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332
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333 // Copy the original liveIns of MBB to NewSuccessor.
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334 for (auto &LI : MBB->liveins())
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335 NewSuccessor->addLiveIn(LI);
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336
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337 // After splitting the NewSuccessor block, Regs defined but not killed
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338 // in MBB should be treated as liveins of NewSuccessor.
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339 // Note: Cannot use stepBackward instead since we are using the Reg
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340 // liveness state at the end of MBB (liveOut of MBB) as the liveIn for
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341 // NewSuccessor. Otherwise, will cause cyclic dependence.
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342 LivePhysRegs LPR(*MF->getSubtarget<PPCSubtarget>().getRegisterInfo());
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343 SmallVector<std::pair<unsigned, const MachineOperand *>, 2> Clobbers;
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344 for (MachineInstr &MI : *MBB)
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345 LPR.stepForward(MI, Clobbers);
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346 for (auto &LI : LPR)
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347 NewSuccessor->addLiveIn(LI);
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348 } else {
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349 // Remove successor from MBB.
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350 MBB->removeSuccessor(Successor);
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351 }
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352
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353 // Note that this needs to be done *after* transfering the successors from MBB
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354 // to the NewSuccessor block, otherwise these blocks will also be transferred
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355 // as successors!
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356 MBB->addSuccessor(IsTrueBlockRequired ? TrueBlock : Successor);
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357 MBB->addSuccessor(IsFalseBlockRequired ? FalseBlock : Successor);
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358
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359 if (IsTrueBlockRequired) {
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360 TrueBlockI = TrueBlock->begin();
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361 TrueBlock->addSuccessor(Successor);
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362 }
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363
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364 if (IsFalseBlockRequired) {
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365 FalseBlockI = FalseBlock->begin();
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366 FalseBlock->addSuccessor(Successor);
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367 }
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368
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369 // Conditional branch to the TrueBlock or Successor
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370 BuildMI(*MBB, BIL.back(), dl, TII->get(PPC::BC))
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371 .add(BIL.back()->getOperand(3))
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372 .addMBB(IsTrueBlockRequired ? TrueBlock : Successor);
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373
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374 // Jump over the true block to the new successor if the condition is false.
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375 BuildMI(*(IsFalseBlockRequired ? FalseBlock : MBB),
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376 (IsFalseBlockRequired ? FalseBlockI : BIL.back()), dl,
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377 TII->get(PPC::B))
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378 .addMBB(Successor);
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379
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380 if (IsFalseBlockRequired)
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381 FalseBlockI = FalseBlock->begin(); // get the position of PPC::B
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382 }
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383
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384 void PPCExpandISEL::populateBlocks(BlockISELList &BIL) {
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385 for (auto &MI : BIL) {
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386 assert(isISEL(*MI) && "Expecting an ISEL instruction");
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387
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388 MachineOperand &Dest = MI->getOperand(0); // location to store to
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389 MachineOperand &TrueValue = MI->getOperand(1); // Value to store if
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390 // condition is true
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391 MachineOperand &FalseValue = MI->getOperand(2); // Value to store if
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392 // condition is false
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393 MachineOperand &ConditionRegister = MI->getOperand(3); // Condition
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394
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395 DEBUG(dbgs() << "Dest: " << Dest << "\n");
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396 DEBUG(dbgs() << "TrueValue: " << TrueValue << "\n");
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397 DEBUG(dbgs() << "FalseValue: " << FalseValue << "\n");
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398 DEBUG(dbgs() << "ConditionRegister: " << ConditionRegister << "\n");
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399
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400
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401 // If the Dest Register and True Value Register are not the same one, we
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402 // need the True Block.
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403 bool IsADDIInstRequired = !useSameRegister(Dest, TrueValue);
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404 bool IsORIInstRequired = !useSameRegister(Dest, FalseValue);
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405
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406 if (IsADDIInstRequired) {
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407 // Copy the result into the destination if the condition is true.
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408 BuildMI(*TrueBlock, TrueBlockI, dl,
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409 TII->get(isISEL8(*MI) ? PPC::ADDI8 : PPC::ADDI))
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410 .add(Dest)
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411 .add(TrueValue)
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412 .add(MachineOperand::CreateImm(0));
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413
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414 // Add the LiveIn registers required by true block.
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415 TrueBlock->addLiveIn(TrueValue.getReg());
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416 }
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417
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418 if (IsORIInstRequired) {
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419 // Add the LiveIn registers required by false block.
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420 FalseBlock->addLiveIn(FalseValue.getReg());
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421 }
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422
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423 if (NewSuccessor) {
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424 // Add the LiveIn registers required by NewSuccessor block.
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425 NewSuccessor->addLiveIn(Dest.getReg());
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426 NewSuccessor->addLiveIn(TrueValue.getReg());
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427 NewSuccessor->addLiveIn(FalseValue.getReg());
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428 NewSuccessor->addLiveIn(ConditionRegister.getReg());
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429 }
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430
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431 // Copy the value into the destination if the condition is false.
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432 if (IsORIInstRequired)
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433 BuildMI(*FalseBlock, FalseBlockI, dl,
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434 TII->get(isISEL8(*MI) ? PPC::ORI8 : PPC::ORI))
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435 .add(Dest)
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436 .add(FalseValue)
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437 .add(MachineOperand::CreateImm(0));
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438
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439 MI->eraseFromParent(); // Remove the ISEL instruction.
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440
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441 NumExpanded++;
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442 }
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443 }
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444
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445 void PPCExpandISEL::expandMergeableISELs(BlockISELList &BIL) {
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446 // At this stage all the ISELs of BIL are in the same MBB.
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447 MachineBasicBlock *MBB = BIL.back()->getParent();
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448
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449 handleSpecialCases(BIL, MBB);
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450 reorganizeBlockLayout(BIL, MBB);
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451 populateBlocks(BIL);
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452 }
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453
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454 INITIALIZE_PASS(PPCExpandISEL, DEBUG_TYPE, "PowerPC Expand ISEL Generation",
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455 false, false)
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456 char PPCExpandISEL::ID = 0;
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457
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458 FunctionPass *llvm::createPPCExpandISELPass() { return new PPCExpandISEL(); }
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