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fix
author mir3636
date Wed, 06 Dec 2017 14:37:17 +0900
parents 1172e4bd9c6f
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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0
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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1 //===- README_X86_64.txt - Notes for X86-64 code gen ----------------------===//
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2
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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3 AMD64 Optimization Manual 8.2 has some nice information about optimizing integer
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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4 multiplication by a constant. How much of it applies to Intel's X86-64
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parents:
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5 implementation? There are definite trade-offs to consider: latency vs. register
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6 pressure vs. code size.
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7
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8 //===---------------------------------------------------------------------===//
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9
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10 Are we better off using branches instead of cmove to implement FP to
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11 unsigned i64?
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12
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13 _conv:
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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14 ucomiss LC0(%rip), %xmm0
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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15 cvttss2siq %xmm0, %rdx
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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16 jb L3
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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17 subss LC0(%rip), %xmm0
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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18 movabsq $-9223372036854775808, %rax
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19 cvttss2siq %xmm0, %rdx
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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20 xorq %rax, %rdx
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21 L3:
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22 movq %rdx, %rax
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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23 ret
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24
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25 instead of
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26
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27 _conv:
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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28 movss LCPI1_0(%rip), %xmm1
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29 cvttss2siq %xmm0, %rcx
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30 movaps %xmm0, %xmm2
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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31 subss %xmm1, %xmm2
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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32 cvttss2siq %xmm2, %rax
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33 movabsq $-9223372036854775808, %rdx
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34 xorq %rdx, %rax
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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35 ucomiss %xmm1, %xmm0
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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36 cmovb %rcx, %rax
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37 ret
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38
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39 Seems like the jb branch has high likelihood of being taken. It would have
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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40 saved a few instructions.
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41
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42 //===---------------------------------------------------------------------===//
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43
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44 It's not possible to reference AH, BH, CH, and DH registers in an instruction
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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45 requiring REX prefix. However, divb and mulb both produce results in AH. If isel
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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46 emits a CopyFromReg which gets turned into a movb and that can be allocated a
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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47 r8b - r15b.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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48
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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49 To get around this, isel emits a CopyFromReg from AX and then right shift it
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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50 down by 8 and truncate it. It's not pretty but it works. We need some register
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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51 allocation magic to make the hack go away (e.g. putting additional constraints
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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52 on the result of the movb).
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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53
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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54 //===---------------------------------------------------------------------===//
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55
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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56 The x86-64 ABI for hidden-argument struct returns requires that the
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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57 incoming value of %rdi be copied into %rax by the callee upon return.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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58
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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59 The idea is that it saves callers from having to remember this value,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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60 which would often require a callee-saved register. Callees usually
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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61 need to keep this value live for most of their body anyway, so it
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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62 doesn't add a significant burden on them.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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63
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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64 We currently implement this in codegen, however this is suboptimal
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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65 because it means that it would be quite awkward to implement the
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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66 optimization for callers.
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67
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68 A better implementation would be to relax the LLVM IR rules for sret
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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69 arguments to allow a function with an sret argument to have a non-void
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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70 return type, and to have the front-end to set up the sret argument value
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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71 as the return value of the function. The front-end could more easily
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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72 emit uses of the returned struct value to be in terms of the function's
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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73 lowered return value, and it would free non-C frontends from a
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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74 complication only required by a C-based ABI.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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75
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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76 //===---------------------------------------------------------------------===//
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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77
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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78 We get a redundant zero extension for code like this:
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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79
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80 int mask[1000];
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81 int foo(unsigned x) {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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82 if (x < 10)
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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83 x = x * 45;
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parents:
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84 else
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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85 x = x * 78;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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86 return mask[x];
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87 }
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88
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89 _foo:
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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90 LBB1_0: ## entry
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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91 cmpl $9, %edi
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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92 jbe LBB1_3 ## bb
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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93 LBB1_1: ## bb1
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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94 imull $78, %edi, %eax
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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95 LBB1_2: ## bb2
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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96 movl %eax, %eax <----
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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97 movq _mask@GOTPCREL(%rip), %rcx
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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98 movl (%rcx,%rax,4), %eax
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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99 ret
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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100 LBB1_3: ## bb
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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101 imull $45, %edi, %eax
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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102 jmp LBB1_2 ## bb2
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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103
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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104 Before regalloc, we have:
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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105
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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106 %reg1025<def> = IMUL32rri8 %reg1024, 45, %EFLAGS<imp-def>
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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107 JMP mbb<bb2,0x203afb0>
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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108 Successors according to CFG: 0x203afb0 (#3)
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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109
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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110 bb1: 0x203af60, LLVM BB @0x1e02310, ID#2:
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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111 Predecessors according to CFG: 0x203aec0 (#0)
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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112 %reg1026<def> = IMUL32rri8 %reg1024, 78, %EFLAGS<imp-def>
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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113 Successors according to CFG: 0x203afb0 (#3)
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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114
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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115 bb2: 0x203afb0, LLVM BB @0x1e02340, ID#3:
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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116 Predecessors according to CFG: 0x203af10 (#1) 0x203af60 (#2)
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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117 %reg1027<def> = PHI %reg1025, mbb<bb,0x203af10>,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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118 %reg1026, mbb<bb1,0x203af60>
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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119 %reg1029<def> = MOVZX64rr32 %reg1027
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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120
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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121 so we'd have to know that IMUL32rri8 leaves the high word zero extended and to
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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122 be able to recognize the zero extend. This could also presumably be implemented
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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123 if we have whole-function selectiondags.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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124
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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125 //===---------------------------------------------------------------------===//
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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126
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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127 Take the following code
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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128 (from http://gcc.gnu.org/bugzilla/show_bug.cgi?id=34653):
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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129 extern unsigned long table[];
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130 unsigned long foo(unsigned char *p) {
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131 unsigned long tag = *p;
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132 return table[tag >> 4] + table[tag & 0xf];
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133 }
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134
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135 Current code generated:
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136 movzbl (%rdi), %eax
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137 movq %rax, %rcx
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138 andq $240, %rcx
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139 shrq %rcx
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140 andq $15, %rax
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141 movq table(,%rax,8), %rax
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142 addq table(%rcx), %rax
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143 ret
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144
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145 Issues:
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146 1. First movq should be movl; saves a byte.
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147 2. Both andq's should be andl; saves another two bytes. I think this was
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148 implemented at one point, but subsequently regressed.
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149 3. shrq should be shrl; saves another byte.
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150 4. The first andq can be completely eliminated by using a slightly more
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151 expensive addressing mode.
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152
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153 //===---------------------------------------------------------------------===//
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154
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155 Consider the following (contrived testcase, but contains common factors):
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156
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157 #include <stdarg.h>
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158 int test(int x, ...) {
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159 int sum, i;
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160 va_list l;
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161 va_start(l, x);
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162 for (i = 0; i < x; i++)
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163 sum += va_arg(l, int);
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164 va_end(l);
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165 return sum;
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166 }
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167
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168 Testcase given in C because fixing it will likely involve changing the IR
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169 generated for it. The primary issue with the result is that it doesn't do any
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170 of the optimizations which are possible if we know the address of a va_list
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171 in the current function is never taken:
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172 1. We shouldn't spill the XMM registers because we only call va_arg with "int".
120
1172e4bd9c6f update 4.0.0
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173 2. It would be nice if we could sroa the va_list.
0
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174 3. Probably overkill, but it'd be cool if we could peel off the first five
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175 iterations of the loop.
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176
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177 Other optimizations involving functions which use va_arg on floats which don't
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178 have the address of a va_list taken:
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179 1. Conversely to the above, we shouldn't spill general registers if we only
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180 call va_arg on "double".
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181 2. If we know nothing more than 64 bits wide is read from the XMM registers,
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182 we can change the spilling code to reduce the amount of stack used by half.
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183
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184 //===---------------------------------------------------------------------===//