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1 //=== X86CallingConv.cpp - X86 Custom Calling Convention Impl -*- C++ -*-===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 // This file contains the implementation of custom routines for the X86
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11 // Calling Convention that aren't done by tablegen.
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12 //
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13 //===----------------------------------------------------------------------===//
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14
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15 #include "MCTargetDesc/X86MCTargetDesc.h"
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16 #include "X86Subtarget.h"
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17 #include "llvm/CodeGen/CallingConvLower.h"
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18 #include "llvm/IR/CallingConv.h"
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19
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20 namespace llvm {
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21
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22 bool CC_X86_32_RegCall_Assign2Regs(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
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23 CCValAssign::LocInfo &LocInfo,
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24 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
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25 // List of GPR registers that are available to store values in regcall
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26 // calling convention.
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27 static const MCPhysReg RegList[] = {X86::EAX, X86::ECX, X86::EDX, X86::EDI,
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28 X86::ESI};
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29
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30 // The vector will save all the available registers for allocation.
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31 SmallVector<unsigned, 5> AvailableRegs;
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32
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33 // searching for the available registers.
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34 for (auto Reg : RegList) {
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35 if (!State.isAllocated(Reg))
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36 AvailableRegs.push_back(Reg);
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37 }
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38
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39 const size_t RequiredGprsUponSplit = 2;
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40 if (AvailableRegs.size() < RequiredGprsUponSplit)
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41 return false; // Not enough free registers - continue the search.
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42
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43 // Allocating the available registers.
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44 for (unsigned I = 0; I < RequiredGprsUponSplit; I++) {
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45
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46 // Marking the register as located.
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47 unsigned Reg = State.AllocateReg(AvailableRegs[I]);
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48
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49 // Since we previously made sure that 2 registers are available
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50 // we expect that a real register number will be returned.
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51 assert(Reg && "Expecting a register will be available");
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52
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53 // Assign the value to the allocated register
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54 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
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55 }
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56
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57 // Successful in allocating regsiters - stop scanning next rules.
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58 return true;
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59 }
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60
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61 static ArrayRef<MCPhysReg> CC_X86_VectorCallGetSSEs(const MVT &ValVT) {
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62 if (ValVT.is512BitVector()) {
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63 static const MCPhysReg RegListZMM[] = {X86::ZMM0, X86::ZMM1, X86::ZMM2,
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64 X86::ZMM3, X86::ZMM4, X86::ZMM5};
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65 return makeArrayRef(std::begin(RegListZMM), std::end(RegListZMM));
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66 }
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67
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68 if (ValVT.is256BitVector()) {
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69 static const MCPhysReg RegListYMM[] = {X86::YMM0, X86::YMM1, X86::YMM2,
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70 X86::YMM3, X86::YMM4, X86::YMM5};
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71 return makeArrayRef(std::begin(RegListYMM), std::end(RegListYMM));
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72 }
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73
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74 static const MCPhysReg RegListXMM[] = {X86::XMM0, X86::XMM1, X86::XMM2,
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75 X86::XMM3, X86::XMM4, X86::XMM5};
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76 return makeArrayRef(std::begin(RegListXMM), std::end(RegListXMM));
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77 }
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78
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79 static ArrayRef<MCPhysReg> CC_X86_64_VectorCallGetGPRs() {
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80 static const MCPhysReg RegListGPR[] = {X86::RCX, X86::RDX, X86::R8, X86::R9};
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81 return makeArrayRef(std::begin(RegListGPR), std::end(RegListGPR));
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82 }
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83
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84 static bool CC_X86_VectorCallAssignRegister(unsigned &ValNo, MVT &ValVT,
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85 MVT &LocVT,
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86 CCValAssign::LocInfo &LocInfo,
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87 ISD::ArgFlagsTy &ArgFlags,
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88 CCState &State) {
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89
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90 ArrayRef<MCPhysReg> RegList = CC_X86_VectorCallGetSSEs(ValVT);
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91 bool Is64bit = static_cast<const X86Subtarget &>(
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92 State.getMachineFunction().getSubtarget())
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93 .is64Bit();
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94
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95 for (auto Reg : RegList) {
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96 // If the register is not marked as allocated - assign to it.
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97 if (!State.isAllocated(Reg)) {
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98 unsigned AssigedReg = State.AllocateReg(Reg);
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99 assert(AssigedReg == Reg && "Expecting a valid register allocation");
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100 State.addLoc(
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101 CCValAssign::getReg(ValNo, ValVT, AssigedReg, LocVT, LocInfo));
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102 return true;
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103 }
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104 // If the register is marked as shadow allocated - assign to it.
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105 if (Is64bit && State.IsShadowAllocatedReg(Reg)) {
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106 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
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107 return true;
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108 }
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109 }
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110
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111 llvm_unreachable("Clang should ensure that hva marked vectors will have "
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112 "an available register.");
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113 return false;
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114 }
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115
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116 bool CC_X86_64_VectorCall(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
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117 CCValAssign::LocInfo &LocInfo,
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118 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
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119 // On the second pass, go through the HVAs only.
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120 if (ArgFlags.isSecArgPass()) {
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121 if (ArgFlags.isHva())
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122 return CC_X86_VectorCallAssignRegister(ValNo, ValVT, LocVT, LocInfo,
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123 ArgFlags, State);
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124 return true;
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125 }
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126
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127 // Process only vector types as defined by vectorcall spec:
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128 // "A vector type is either a floating-point type, for example,
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129 // a float or double, or an SIMD vector type, for example, __m128 or __m256".
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130 if (!(ValVT.isFloatingPoint() ||
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131 (ValVT.isVector() && ValVT.getSizeInBits() >= 128))) {
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132 // If R9 was already assigned it means that we are after the fourth element
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133 // and because this is not an HVA / Vector type, we need to allocate
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134 // shadow XMM register.
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135 if (State.isAllocated(X86::R9)) {
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136 // Assign shadow XMM register.
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137 (void)State.AllocateReg(CC_X86_VectorCallGetSSEs(ValVT));
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138 }
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139
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140 return false;
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141 }
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142
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143 if (!ArgFlags.isHva() || ArgFlags.isHvaStart()) {
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144 // Assign shadow GPR register.
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145 (void)State.AllocateReg(CC_X86_64_VectorCallGetGPRs());
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146
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147 // Assign XMM register - (shadow for HVA and non-shadow for non HVA).
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148 if (unsigned Reg = State.AllocateReg(CC_X86_VectorCallGetSSEs(ValVT))) {
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149 // In Vectorcall Calling convention, additional shadow stack can be
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150 // created on top of the basic 32 bytes of win64.
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151 // It can happen if the fifth or sixth argument is vector type or HVA.
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152 // At that case for each argument a shadow stack of 8 bytes is allocated.
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153 if (Reg == X86::XMM4 || Reg == X86::XMM5)
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154 State.AllocateStack(8, 8);
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155
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156 if (!ArgFlags.isHva()) {
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157 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
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158 return true; // Allocated a register - Stop the search.
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159 }
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160 }
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161 }
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162
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163 // If this is an HVA - Stop the search,
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164 // otherwise continue the search.
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165 return ArgFlags.isHva();
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166 }
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167
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168 bool CC_X86_32_VectorCall(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
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169 CCValAssign::LocInfo &LocInfo,
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170 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
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171 // On the second pass, go through the HVAs only.
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172 if (ArgFlags.isSecArgPass()) {
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173 if (ArgFlags.isHva())
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174 return CC_X86_VectorCallAssignRegister(ValNo, ValVT, LocVT, LocInfo,
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175 ArgFlags, State);
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176 return true;
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177 }
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178
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179 // Process only vector types as defined by vectorcall spec:
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180 // "A vector type is either a floating point type, for example,
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181 // a float or double, or an SIMD vector type, for example, __m128 or __m256".
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182 if (!(ValVT.isFloatingPoint() ||
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183 (ValVT.isVector() && ValVT.getSizeInBits() >= 128))) {
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184 return false;
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185 }
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186
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187 if (ArgFlags.isHva())
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188 return true; // If this is an HVA - Stop the search.
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189
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190 // Assign XMM register.
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191 if (unsigned Reg = State.AllocateReg(CC_X86_VectorCallGetSSEs(ValVT))) {
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192 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
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193 return true;
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194 }
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195
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196 // In case we did not find an available XMM register for a vector -
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197 // pass it indirectly.
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198 // It is similar to CCPassIndirect, with the addition of inreg.
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199 if (!ValVT.isFloatingPoint()) {
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200 LocVT = MVT::i32;
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201 LocInfo = CCValAssign::Indirect;
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202 ArgFlags.setInReg();
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203 }
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204
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205 return false; // No register was assigned - Continue the search.
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206 }
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207
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208 } // End llvm namespace
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