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fix
author mir3636
date Wed, 06 Dec 2017 14:37:17 +0900
parents 803732b1fca8
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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1 //===-- X86InstrControl.td - Control Flow Instructions -----*- tablegen -*-===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 // This file describes the X86 jump, return, call, and related instructions.
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11 //
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12 //===----------------------------------------------------------------------===//
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13
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14 //===----------------------------------------------------------------------===//
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15 // Control Flow Instructions.
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16 //
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17
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18 // Return instructions.
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19 //
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20 // The X86retflag return instructions are variadic because we may add ST0 and
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21 // ST1 arguments when returning values on the x87 stack.
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22 let isTerminator = 1, isReturn = 1, isBarrier = 1,
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23 hasCtrlDep = 1, FPForm = SpecialFP, SchedRW = [WriteJumpLd] in {
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24 def RETL : I <0xC3, RawFrm, (outs), (ins variable_ops),
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25 "ret{l}", [], IIC_RET>, OpSize32,
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26 Requires<[Not64BitMode]>;
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27 def RETQ : I <0xC3, RawFrm, (outs), (ins variable_ops),
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28 "ret{q}", [], IIC_RET>, OpSize32,
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29 Requires<[In64BitMode]>;
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30 def RETW : I <0xC3, RawFrm, (outs), (ins),
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31 "ret{w}",
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32 [], IIC_RET>, OpSize16;
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33 def RETIL : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
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34 "ret{l}\t$amt",
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35 [], IIC_RET_IMM>, OpSize32,
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36 Requires<[Not64BitMode]>;
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37 def RETIQ : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
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38 "ret{q}\t$amt",
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39 [], IIC_RET_IMM>, OpSize32,
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40 Requires<[In64BitMode]>;
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41 def RETIW : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt),
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42 "ret{w}\t$amt",
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43 [], IIC_RET_IMM>, OpSize16;
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44 def LRETL : I <0xCB, RawFrm, (outs), (ins),
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45 "{l}ret{l|f}", [], IIC_RET>, OpSize32;
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46 def LRETQ : RI <0xCB, RawFrm, (outs), (ins),
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47 "{l}ret{|f}q", [], IIC_RET>, Requires<[In64BitMode]>;
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48 def LRETW : I <0xCB, RawFrm, (outs), (ins),
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49 "{l}ret{w|f}", [], IIC_RET>, OpSize16;
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50 def LRETIL : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
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51 "{l}ret{l|f}\t$amt", [], IIC_RET>, OpSize32;
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52 def LRETIQ : RIi16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
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53 "{l}ret{|f}q\t$amt", [], IIC_RET>, Requires<[In64BitMode]>;
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54 def LRETIW : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
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55 "{l}ret{w|f}\t$amt", [], IIC_RET>, OpSize16;
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56
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57 // The machine return from interrupt instruction, but sometimes we need to
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58 // perform a post-epilogue stack adjustment. Codegen emits the pseudo form
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59 // which expands to include an SP adjustment if necessary.
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60 def IRET16 : I <0xcf, RawFrm, (outs), (ins), "iret{w}", [], IIC_IRET>,
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61 OpSize16;
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62 def IRET32 : I <0xcf, RawFrm, (outs), (ins), "iret{l|d}", [],
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63 IIC_IRET>, OpSize32;
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64 def IRET64 : RI <0xcf, RawFrm, (outs), (ins), "iretq", [],
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65 IIC_IRET>, Requires<[In64BitMode]>;
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66 let isCodeGenOnly = 1 in
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67 def IRET : PseudoI<(outs), (ins i32imm:$adj), [(X86iret timm:$adj)]>;
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68 def RET : PseudoI<(outs), (ins i32imm:$adj, variable_ops), [(X86retflag timm:$adj)]>;
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69 }
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70
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71 // Unconditional branches.
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72 let isBarrier = 1, isBranch = 1, isTerminator = 1, SchedRW = [WriteJump] in {
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73 def JMP_1 : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst),
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74 "jmp\t$dst", [(br bb:$dst)], IIC_JMP_REL>;
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75 let hasSideEffects = 0, isCodeGenOnly = 1, ForceDisassemble = 1 in {
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76 def JMP_2 : Ii16PCRel<0xE9, RawFrm, (outs), (ins brtarget16:$dst),
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77 "jmp\t$dst", [], IIC_JMP_REL>, OpSize16;
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78 def JMP_4 : Ii32PCRel<0xE9, RawFrm, (outs), (ins brtarget32:$dst),
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79 "jmp\t$dst", [], IIC_JMP_REL>, OpSize32;
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80 }
0
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81 }
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82
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83 // Conditional Branches.
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84 let isBranch = 1, isTerminator = 1, Uses = [EFLAGS], SchedRW = [WriteJump] in {
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85 multiclass ICBr<bits<8> opc1, bits<8> opc4, string asm, PatFrag Cond> {
83
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86 def _1 : Ii8PCRel <opc1, RawFrm, (outs), (ins brtarget8:$dst), asm,
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87 [(X86brcond bb:$dst, Cond, EFLAGS)], IIC_Jcc>;
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88 let hasSideEffects = 0, isCodeGenOnly = 1, ForceDisassemble = 1 in {
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89 def _2 : Ii16PCRel<opc4, RawFrm, (outs), (ins brtarget16:$dst), asm,
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90 [], IIC_Jcc>, OpSize16, TB;
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91 def _4 : Ii32PCRel<opc4, RawFrm, (outs), (ins brtarget32:$dst), asm,
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92 [], IIC_Jcc>, TB, OpSize32;
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93 }
0
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94 }
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95 }
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96
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97 defm JO : ICBr<0x70, 0x80, "jo\t$dst" , X86_COND_O>;
83
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98 defm JNO : ICBr<0x71, 0x81, "jno\t$dst", X86_COND_NO>;
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99 defm JB : ICBr<0x72, 0x82, "jb\t$dst" , X86_COND_B>;
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100 defm JAE : ICBr<0x73, 0x83, "jae\t$dst", X86_COND_AE>;
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101 defm JE : ICBr<0x74, 0x84, "je\t$dst" , X86_COND_E>;
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102 defm JNE : ICBr<0x75, 0x85, "jne\t$dst", X86_COND_NE>;
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103 defm JBE : ICBr<0x76, 0x86, "jbe\t$dst", X86_COND_BE>;
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104 defm JA : ICBr<0x77, 0x87, "ja\t$dst" , X86_COND_A>;
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105 defm JS : ICBr<0x78, 0x88, "js\t$dst" , X86_COND_S>;
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106 defm JNS : ICBr<0x79, 0x89, "jns\t$dst", X86_COND_NS>;
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107 defm JP : ICBr<0x7A, 0x8A, "jp\t$dst" , X86_COND_P>;
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108 defm JNP : ICBr<0x7B, 0x8B, "jnp\t$dst", X86_COND_NP>;
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109 defm JL : ICBr<0x7C, 0x8C, "jl\t$dst" , X86_COND_L>;
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110 defm JGE : ICBr<0x7D, 0x8D, "jge\t$dst", X86_COND_GE>;
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111 defm JLE : ICBr<0x7E, 0x8E, "jle\t$dst", X86_COND_LE>;
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112 defm JG : ICBr<0x7F, 0x8F, "jg\t$dst" , X86_COND_G>;
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113
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114 // jcx/jecx/jrcx instructions.
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115 let isBranch = 1, isTerminator = 1, hasSideEffects = 0, SchedRW = [WriteJump] in {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
116 // These are the 32-bit versions of this instruction for the asmparser. In
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
117 // 32-bit mode, the address size prefix is jcxz and the unprefixed version is
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
118 // jecxz.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
119 let Uses = [CX] in
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
120 def JCXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
121 "jcxz\t$dst", [], IIC_JCXZ>, AdSize16,
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
122 Requires<[Not64BitMode]>;
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
123 let Uses = [ECX] in
83
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
124 def JECXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
125 "jecxz\t$dst", [], IIC_JCXZ>, AdSize32;
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
126
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
127 let Uses = [RCX] in
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
128 def JRCXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
129 "jrcxz\t$dst", [], IIC_JCXZ>, AdSize64,
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
130 Requires<[In64BitMode]>;
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
131 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
132
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
133 // Indirect branches
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
134 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
135 def JMP16r : I<0xFF, MRM4r, (outs), (ins GR16:$dst), "jmp{w}\t{*}$dst",
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
136 [(brind GR16:$dst)], IIC_JMP_REG>, Requires<[Not64BitMode]>,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
137 OpSize16, Sched<[WriteJump]>;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
138 def JMP16m : I<0xFF, MRM4m, (outs), (ins i16mem:$dst), "jmp{w}\t{*}$dst",
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
139 [(brind (loadi16 addr:$dst))], IIC_JMP_MEM>,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
140 Requires<[Not64BitMode]>, OpSize16, Sched<[WriteJumpLd]>;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
141
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
142 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
143 [(brind GR32:$dst)], IIC_JMP_REG>, Requires<[Not64BitMode]>,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
144 OpSize32, Sched<[WriteJump]>;
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
145 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
146 [(brind (loadi32 addr:$dst))], IIC_JMP_MEM>,
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
147 Requires<[Not64BitMode]>, OpSize32, Sched<[WriteJumpLd]>;
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
148
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
149 def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst",
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
150 [(brind GR64:$dst)], IIC_JMP_REG>, Requires<[In64BitMode]>,
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
151 Sched<[WriteJump]>;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
152 def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst",
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
153 [(brind (loadi64 addr:$dst))], IIC_JMP_MEM>,
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
154 Requires<[In64BitMode]>, Sched<[WriteJumpLd]>;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
155
83
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
156 let Predicates = [Not64BitMode] in {
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
157 def FARJMP16i : Iseg16<0xEA, RawFrmImm16, (outs),
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
158 (ins i16imm:$off, i16imm:$seg),
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
159 "ljmp{w}\t$seg, $off", [],
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
160 IIC_JMP_FAR_PTR>, OpSize16, Sched<[WriteJump]>;
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
161 def FARJMP32i : Iseg32<0xEA, RawFrmImm16, (outs),
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
162 (ins i32imm:$off, i16imm:$seg),
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
163 "ljmp{l}\t$seg, $off", [],
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
164 IIC_JMP_FAR_PTR>, OpSize32, Sched<[WriteJump]>;
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
165 }
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
166 def FARJMP64 : RI<0xFF, MRM5m, (outs), (ins opaque80mem:$dst),
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
167 "ljmp{q}\t{*}$dst", [], IIC_JMP_FAR_MEM>,
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
168 Sched<[WriteJump]>;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
169
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
170 def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaque32mem:$dst),
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
171 "ljmp{w}\t{*}$dst", [], IIC_JMP_FAR_MEM>, OpSize16,
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
172 Sched<[WriteJumpLd]>;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
173 def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaque48mem:$dst),
121
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
174 "{l}jmp{l}\t{*}$dst", [], IIC_JMP_FAR_MEM>, OpSize32,
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
175 Sched<[WriteJumpLd]>;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
176 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
177
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
178
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
179 // Loop instructions
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
180 let SchedRW = [WriteJump] in {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
181 def LOOP : Ii8PCRel<0xE2, RawFrm, (outs), (ins brtarget8:$dst), "loop\t$dst", [], IIC_LOOP>;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
182 def LOOPE : Ii8PCRel<0xE1, RawFrm, (outs), (ins brtarget8:$dst), "loope\t$dst", [], IIC_LOOPE>;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
183 def LOOPNE : Ii8PCRel<0xE0, RawFrm, (outs), (ins brtarget8:$dst), "loopne\t$dst", [], IIC_LOOPNE>;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
184 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
185
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
186 //===----------------------------------------------------------------------===//
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
187 // Call Instructions...
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
188 //
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
189 let isCall = 1 in
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
190 // All calls clobber the non-callee saved registers. ESP is marked as
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
191 // a use to prevent stack-pointer assignments that appear immediately
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
192 // before calls from potentially appearing dead. Uses for argument
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
193 // registers are added manually.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
194 let Uses = [ESP] in {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
195 def CALLpcrel32 : Ii32PCRel<0xE8, RawFrm,
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
196 (outs), (ins i32imm_pcrel:$dst),
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
197 "call{l}\t$dst", [], IIC_CALL_RI>, OpSize32,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
198 Requires<[Not64BitMode]>, Sched<[WriteJump]>;
83
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
199 let hasSideEffects = 0 in
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
200 def CALLpcrel16 : Ii16PCRel<0xE8, RawFrm,
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
201 (outs), (ins i16imm_pcrel:$dst),
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
202 "call{w}\t$dst", [], IIC_CALL_RI>, OpSize16,
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
203 Sched<[WriteJump]>;
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
204 def CALL16r : I<0xFF, MRM2r, (outs), (ins GR16:$dst),
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
205 "call{w}\t{*}$dst", [(X86call GR16:$dst)], IIC_CALL_RI>,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
206 OpSize16, Requires<[Not64BitMode]>, Sched<[WriteJump]>;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
207 def CALL16m : I<0xFF, MRM2m, (outs), (ins i16mem:$dst),
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
208 "call{w}\t{*}$dst", [(X86call (loadi16 addr:$dst))],
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
209 IIC_CALL_MEM>, OpSize16,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
210 Requires<[Not64BitMode,FavorMemIndirectCall]>,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
211 Sched<[WriteJumpLd]>;
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
212 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst),
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
213 "call{l}\t{*}$dst", [(X86call GR32:$dst)], IIC_CALL_RI>,
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
214 OpSize32, Requires<[Not64BitMode]>, Sched<[WriteJump]>;
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
215 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst),
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
216 "call{l}\t{*}$dst", [(X86call (loadi32 addr:$dst))],
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
217 IIC_CALL_MEM>, OpSize32,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
218 Requires<[Not64BitMode,FavorMemIndirectCall]>,
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
219 Sched<[WriteJumpLd]>;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
220
83
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
221 let Predicates = [Not64BitMode] in {
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
222 def FARCALL16i : Iseg16<0x9A, RawFrmImm16, (outs),
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
223 (ins i16imm:$off, i16imm:$seg),
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
224 "lcall{w}\t$seg, $off", [],
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
225 IIC_CALL_FAR_PTR>, OpSize16, Sched<[WriteJump]>;
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
226 def FARCALL32i : Iseg32<0x9A, RawFrmImm16, (outs),
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
227 (ins i32imm:$off, i16imm:$seg),
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
228 "lcall{l}\t$seg, $off", [],
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
229 IIC_CALL_FAR_PTR>, OpSize32, Sched<[WriteJump]>;
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
230 }
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
231
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
232 def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaque32mem:$dst),
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
233 "lcall{w}\t{*}$dst", [], IIC_CALL_FAR_MEM>, OpSize16,
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
234 Sched<[WriteJumpLd]>;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
235 def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaque48mem:$dst),
121
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
236 "{l}call{l}\t{*}$dst", [], IIC_CALL_FAR_MEM>, OpSize32,
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
237 Sched<[WriteJumpLd]>;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
238 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
239
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
240
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
241 // Tail call stuff.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
242 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
243 isCodeGenOnly = 1, SchedRW = [WriteJumpLd] in
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
244 let Uses = [ESP] in {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
245 def TCRETURNdi : PseudoI<(outs),
121
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
246 (ins i32imm_pcrel:$dst, i32imm:$offset), []>, NotMemoryFoldable;
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
247 def TCRETURNri : PseudoI<(outs),
121
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
248 (ins ptr_rc_tailcall:$dst, i32imm:$offset), []>, NotMemoryFoldable;
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
249 let mayLoad = 1 in
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
250 def TCRETURNmi : PseudoI<(outs),
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
251 (ins i32mem_TC:$dst, i32imm:$offset), []>;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
252
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
253 // FIXME: The should be pseudo instructions that are lowered when going to
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
254 // mcinst.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
255 def TAILJMPd : Ii32PCRel<0xE9, RawFrm, (outs),
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
256 (ins i32imm_pcrel:$dst),
83
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
257 "jmp\t$dst",
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
258 [], IIC_JMP_REL>;
120
1172e4bd9c6f update 4.0.0
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parents: 100
diff changeset
259
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
260 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins ptr_rc_tailcall:$dst),
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
261 "", [], IIC_JMP_REG>; // FIXME: Remove encoding when JIT is dead.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
262 let mayLoad = 1 in
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
263 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem_TC:$dst),
83
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
264 "jmp{l}\t{*}$dst", [], IIC_JMP_MEM>;
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
265 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
266
120
1172e4bd9c6f update 4.0.0
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diff changeset
267 // Conditional tail calls are similar to the above, but they are branches
1172e4bd9c6f update 4.0.0
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diff changeset
268 // rather than barriers, and they use EFLAGS.
1172e4bd9c6f update 4.0.0
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parents: 100
diff changeset
269 let isCall = 1, isTerminator = 1, isReturn = 1, isBranch = 1,
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
270 isCodeGenOnly = 1, SchedRW = [WriteJumpLd] in
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
271 let Uses = [ESP, EFLAGS] in {
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
272 def TCRETURNdicc : PseudoI<(outs),
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
273 (ins i32imm_pcrel:$dst, i32imm:$offset, i32imm:$cond), []>;
1172e4bd9c6f update 4.0.0
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parents: 100
diff changeset
274
1172e4bd9c6f update 4.0.0
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parents: 100
diff changeset
275 // This gets substituted to a conditional jump instruction in MC lowering.
1172e4bd9c6f update 4.0.0
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parents: 100
diff changeset
276 def TAILJMPd_CC : Ii32PCRel<0x80, RawFrm, (outs),
1172e4bd9c6f update 4.0.0
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parents: 100
diff changeset
277 (ins i32imm_pcrel:$dst, i32imm:$cond),
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
278 "",
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
279 [], IIC_JMP_REL>;
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
280 }
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
281
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
282
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
283 //===----------------------------------------------------------------------===//
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
284 // Call Instructions...
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
285 //
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
286
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
287 // RSP is marked as a use to prevent stack-pointer assignments that appear
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
288 // immediately before calls from potentially appearing dead. Uses for argument
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
289 // registers are added manually.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
290 let isCall = 1, Uses = [RSP], SchedRW = [WriteJump] in {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
291 // NOTE: this pattern doesn't match "X86call imm", because we do not know
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
292 // that the offset between an arbitrary immediate and the call will fit in
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
293 // the 32-bit pcrel field that we have.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
294 def CALL64pcrel32 : Ii32PCRel<0xE8, RawFrm,
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
295 (outs), (ins i64i32imm_pcrel:$dst),
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
296 "call{q}\t$dst", [], IIC_CALL_RI>, OpSize32,
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
297 Requires<[In64BitMode]>;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
298 def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst),
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
299 "call{q}\t{*}$dst", [(X86call GR64:$dst)],
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
300 IIC_CALL_RI>,
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
301 Requires<[In64BitMode]>;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
302 def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst),
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
303 "call{q}\t{*}$dst", [(X86call (loadi64 addr:$dst))],
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
304 IIC_CALL_MEM>,
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
305 Requires<[In64BitMode,FavorMemIndirectCall]>;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
306
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
307 def FARCALL64 : RI<0xFF, MRM3m, (outs), (ins opaque80mem:$dst),
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
308 "lcall{q}\t{*}$dst", [], IIC_CALL_FAR_MEM>;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
309 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
310
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
311 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
312 isCodeGenOnly = 1, Uses = [RSP], usesCustomInserter = 1,
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
313 SchedRW = [WriteJump] in {
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
314 def TCRETURNdi64 : PseudoI<(outs),
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
315 (ins i64i32imm_pcrel:$dst, i32imm:$offset),
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
316 []>;
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
317 def TCRETURNri64 : PseudoI<(outs),
121
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
318 (ins ptr_rc_tailcall:$dst, i32imm:$offset), []>, NotMemoryFoldable;
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
319 let mayLoad = 1 in
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
320 def TCRETURNmi64 : PseudoI<(outs),
121
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
321 (ins i64mem_TC:$dst, i32imm:$offset), []>, NotMemoryFoldable;
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
322
83
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
323 def TAILJMPd64 : Ii32PCRel<0xE9, RawFrm, (outs), (ins i64i32imm_pcrel:$dst),
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
324 "jmp\t$dst", [], IIC_JMP_REL>;
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
325
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
326 def TAILJMPr64 : I<0xFF, MRM4r, (outs), (ins ptr_rc_tailcall:$dst),
83
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
327 "jmp{q}\t{*}$dst", [], IIC_JMP_MEM>;
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
328
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
329 let mayLoad = 1 in
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
330 def TAILJMPm64 : I<0xFF, MRM4m, (outs), (ins i64mem_TC:$dst),
83
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
331 "jmp{q}\t{*}$dst", [], IIC_JMP_MEM>;
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
332
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
333 // Win64 wants indirect jumps leaving the function to have a REX_W prefix.
83
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
334 let hasREX_WPrefix = 1 in {
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
335 def TAILJMPr64_REX : I<0xFF, MRM4r, (outs), (ins ptr_rc_tailcall:$dst),
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
336 "rex64 jmp{q}\t{*}$dst", [], IIC_JMP_MEM>;
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
337
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
338 let mayLoad = 1 in
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
339 def TAILJMPm64_REX : I<0xFF, MRM4m, (outs), (ins i64mem_TC:$dst),
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
340 "rex64 jmp{q}\t{*}$dst", [], IIC_JMP_MEM>;
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
341 }
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
342 }
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
343
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
344 // Conditional tail calls are similar to the above, but they are branches
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
345 // rather than barriers, and they use EFLAGS.
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
346 let isCall = 1, isTerminator = 1, isReturn = 1, isBranch = 1,
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
347 isCodeGenOnly = 1, SchedRW = [WriteJumpLd] in
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
348 let Uses = [RSP, EFLAGS] in {
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
349 def TCRETURNdi64cc : PseudoI<(outs),
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
350 (ins i64i32imm_pcrel:$dst, i32imm:$offset,
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
351 i32imm:$cond), []>;
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
352
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
353 // This gets substituted to a conditional jump instruction in MC lowering.
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
354 def TAILJMPd64_CC : Ii32PCRel<0x80, RawFrm, (outs),
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
355 (ins i64i32imm_pcrel:$dst, i32imm:$cond),
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
356 "",
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
357 [], IIC_JMP_REL>;
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
358 }