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1 //===-- X86Subtarget.h - Define Subtarget for the X86 ----------*- C++ -*--===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 // This file declares the X86 specific subclass of TargetSubtargetInfo.
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11 //
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12 //===----------------------------------------------------------------------===//
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13
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77
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14 #ifndef LLVM_LIB_TARGET_X86_X86SUBTARGET_H
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|
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15 #define LLVM_LIB_TARGET_X86_X86SUBTARGET_H
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16
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77
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17 #include "X86FrameLowering.h"
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|
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18 #include "X86ISelLowering.h"
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|
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19 #include "X86InstrInfo.h"
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|
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20 #include "X86SelectionDAGInfo.h"
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121
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21 #include "llvm/ADT/StringRef.h"
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22 #include "llvm/ADT/Triple.h"
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121
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23 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
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|
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24 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
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|
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25 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
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|
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26 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
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27 #include "llvm/IR/CallingConv.h"
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121
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28 #include "llvm/MC/MCInstrItineraries.h"
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|
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29 #include "llvm/Target/TargetMachine.h"
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30 #include "llvm/Target/TargetSubtargetInfo.h"
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121
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31 #include <memory>
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32
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33 #define GET_SUBTARGETINFO_HEADER
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34 #include "X86GenSubtargetInfo.inc"
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35
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36 namespace llvm {
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|
121
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37
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38 class GlobalValue;
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39
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83
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40 /// The X86 backend supports a number of different styles of PIC.
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41 ///
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42 namespace PICStyles {
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121
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43
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44 enum Style {
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120
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45 StubPIC, // Used on i386-darwin in pic mode.
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46 GOT, // Used on 32 bit elf on when in pic mode.
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47 RIPRel, // Used on X86-64 when in pic mode.
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48 None // Set when not in pic mode.
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49 };
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121
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50
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51 } // end namespace PICStyles
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52
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53 class X86Subtarget final : public X86GenSubtargetInfo {
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54 protected:
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55 enum X86SSEEnum {
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95
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56 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
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57 };
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58
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59 enum X863DNowEnum {
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100
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60 NoThreeDNow, MMX, ThreeDNow, ThreeDNowA
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61 };
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62
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63 enum X86ProcFamilyEnum {
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121
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64 Others,
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65 IntelAtom,
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66 IntelSLM,
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67 IntelGLM,
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68 IntelHaswell,
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69 IntelBroadwell,
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70 IntelSkylake,
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71 IntelKNL,
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72 IntelSKX,
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73 IntelCannonlake
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74 };
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75
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83
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76 /// X86 processor family: Intel Atom, and others
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77 X86ProcFamilyEnum X86ProcFamily;
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78
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83
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79 /// Which PIC style to use
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80 PICStyles::Style PICStyle;
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81
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120
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82 const TargetMachine &TM;
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|
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83
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95
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84 /// SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or none supported.
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85 X86SSEEnum X86SSELevel;
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86
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100
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87 /// MMX, 3DNow, 3DNow Athlon, or none supported.
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88 X863DNowEnum X863DNowLevel;
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89
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120
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90 /// True if the processor supports X87 instructions.
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|
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91 bool HasX87;
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|
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92
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83
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93 /// True if this processor has conditional move instructions
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94 /// (generally pentium pro+).
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95 bool HasCMov;
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96
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83
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97 /// True if the processor supports X86-64 instructions.
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98 bool HasX86_64;
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99
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83
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100 /// True if the processor supports POPCNT.
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101 bool HasPOPCNT;
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102
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83
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103 /// True if the processor supports SSE4A instructions.
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104 bool HasSSE4A;
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105
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83
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106 /// Target has AES instructions
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107 bool HasAES;
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108
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100
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109 /// Target has FXSAVE/FXRESTOR instructions
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|
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110 bool HasFXSR;
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|
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111
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95
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112 /// Target has XSAVE instructions
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113 bool HasXSAVE;
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121
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114
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95
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115 /// Target has XSAVEOPT instructions
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116 bool HasXSAVEOPT;
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|
121
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117
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95
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118 /// Target has XSAVEC instructions
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119 bool HasXSAVEC;
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|
121
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120
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95
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121 /// Target has XSAVES instructions
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|
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122 bool HasXSAVES;
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123
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83
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124 /// Target has carry-less multiplication
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125 bool HasPCLMUL;
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126
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83
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127 /// Target has 3-operand fused multiply-add
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128 bool HasFMA;
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129
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83
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130 /// Target has 4-operand fused multiply-add
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131 bool HasFMA4;
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132
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83
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133 /// Target has XOP instructions
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134 bool HasXOP;
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135
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83
|
136 /// Target has TBM instructions.
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137 bool HasTBM;
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138
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|
121
|
139 /// Target has LWP instructions
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|
|
140 bool HasLWP;
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|
|
141
|
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83
|
142 /// True if the processor has the MOVBE instruction.
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143 bool HasMOVBE;
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144
|
|
83
|
145 /// True if the processor has the RDRAND instruction.
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146 bool HasRDRAND;
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147
|
|
83
|
148 /// Processor has 16-bit floating point conversion instructions.
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149 bool HasF16C;
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150
|
|
83
|
151 /// Processor has FS/GS base insturctions.
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152 bool HasFSGSBase;
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153
|
|
83
|
154 /// Processor has LZCNT instruction.
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155 bool HasLZCNT;
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156
|
|
83
|
157 /// Processor has BMI1 instructions.
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158 bool HasBMI;
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159
|
|
83
|
160 /// Processor has BMI2 instructions.
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161 bool HasBMI2;
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162
|
|
100
|
163 /// Processor has VBMI instructions.
|
|
|
164 bool HasVBMI;
|
|
|
165
|
|
|
166 /// Processor has Integer Fused Multiply Add
|
|
|
167 bool HasIFMA;
|
|
|
168
|
|
83
|
169 /// Processor has RTM instructions.
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170 bool HasRTM;
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171
|
|
83
|
172 /// Processor has ADX instructions.
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173 bool HasADX;
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174
|
|
83
|
175 /// Processor has SHA instructions.
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176 bool HasSHA;
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177
|
|
83
|
178 /// Processor has PRFCHW instructions.
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179 bool HasPRFCHW;
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180
|
|
83
|
181 /// Processor has RDSEED instructions.
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182 bool HasRDSEED;
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183
|
|
100
|
184 /// Processor has LAHF/SAHF instructions.
|
|
|
185 bool HasLAHFSAHF;
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|
|
186
|
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120
|
187 /// Processor has MONITORX/MWAITX instructions.
|
|
|
188 bool HasMWAITX;
|
|
|
189
|
|
121
|
190 /// Processor has Cache Line Zero instruction
|
|
|
191 bool HasCLZERO;
|
|
|
192
|
|
100
|
193 /// Processor has Prefetch with intent to Write instruction
|
|
|
194 bool HasPFPREFETCHWT1;
|
|
|
195
|
|
83
|
196 /// True if SHLD instructions are slow.
|
|
33
|
197 bool IsSHLDSlow;
|
|
|
198
|
|
121
|
199 /// True if the PMULLD instruction is slow compared to PMULLW/PMULHW and
|
|
|
200 // PMULUDQ.
|
|
|
201 bool IsPMULLDSlow;
|
|
|
202
|
|
95
|
203 /// True if unaligned memory accesses of 16-bytes are slow.
|
|
|
204 bool IsUAMem16Slow;
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205
|
|
95
|
206 /// True if unaligned memory accesses of 32-bytes are slow.
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|
83
|
207 bool IsUAMem32Slow;
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208
|
|
83
|
209 /// True if SSE operations can have unaligned memory operands.
|
|
|
210 /// This may require setting a configuration bit in the processor.
|
|
|
211 bool HasSSEUnalignedMem;
|
|
|
212
|
|
|
213 /// True if this processor has the CMPXCHG16B instruction;
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214 /// this is true for most x86-64 chips, but not the first AMD chips.
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215 bool HasCmpxchg16b;
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216
|
|
83
|
217 /// True if the LEA instruction should be used for adjusting
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|
218 /// the stack pointer. This is an optimization for Intel Atom processors.
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|
219 bool UseLeaForSP;
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220
|
|
120
|
221 /// True if there is no performance penalty to writing only the lower parts
|
|
121
|
222 /// of a YMM or ZMM register without clearing the upper part.
|
|
|
223 bool HasFastPartialYMMorZMMWrite;
|
|
120
|
224
|
|
|
225 /// True if hardware SQRTSS instruction is at least as fast (latency) as
|
|
|
226 /// RSQRTSS followed by a Newton-Raphson iteration.
|
|
|
227 bool HasFastScalarFSQRT;
|
|
|
228
|
|
|
229 /// True if hardware SQRTPS/VSQRTPS instructions are at least as fast
|
|
|
230 /// (throughput) as RSQRTPS/VRSQRTPS followed by a Newton-Raphson iteration.
|
|
|
231 bool HasFastVectorFSQRT;
|
|
|
232
|
|
83
|
233 /// True if 8-bit divisions are significantly faster than
|
|
|
234 /// 32-bit divisions and should be used when possible.
|
|
|
235 bool HasSlowDivide32;
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236
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121
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237 /// True if 32-bit divides are significantly faster than
|
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83
|
238 /// 64-bit divisions and should be used when possible.
|
|
|
239 bool HasSlowDivide64;
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|
|
240
|
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120
|
241 /// True if LZCNT instruction is fast.
|
|
|
242 bool HasFastLZCNT;
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|
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243
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|
121
|
244 /// True if SHLD based rotate is fast.
|
|
|
245 bool HasFastSHLDRotate;
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246
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|
|
247 /// True if the processor supports macrofusion.
|
|
|
248 bool HasMacroFusion;
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249
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|
|
250 /// True if the processor has enhanced REP MOVSB/STOSB.
|
|
|
251 bool HasERMSB;
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252
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83
|
253 /// True if the short functions should be padded to prevent
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254 /// a stall when returning too early.
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255 bool PadShortFunctions;
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256
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|
121
|
257 /// True if two memory operand instructions should use a temporary register
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|
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258 /// instead.
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|
|
259 bool SlowTwoMemOps;
|
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83
|
260
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|
|
261 /// True if the LEA instruction inputs have to be ready at address generation
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|
262 /// (AG) time.
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263 bool LEAUsesAG;
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264
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83
|
265 /// True if the LEA instruction with certain arguments is slow
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77
|
266 bool SlowLEA;
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267
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121
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268 /// True if the LEA instruction has all three source operands: base, index,
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269 /// and offset or if the LEA instruction uses base and index registers where
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270 /// the base is EBP, RBP,or R13
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271 bool Slow3OpsLEA;
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272
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83
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273 /// True if INC and DEC instructions are slow when writing to flags
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77
|
274 bool SlowIncDec;
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275
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276 /// Processor has AVX-512 PreFetch Instructions
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277 bool HasPFI;
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|
77
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278
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279 /// Processor has AVX-512 Exponential and Reciprocal Instructions
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280 bool HasERI;
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|
77
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281
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282 /// Processor has AVX-512 Conflict Detection Instructions
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283 bool HasCDI;
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|
77
|
284
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121
|
285 /// Processor has AVX-512 population count Instructions
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|
|
286 bool HasVPOPCNTDQ;
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287
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77
|
288 /// Processor has AVX-512 Doubleword and Quadword instructions
|
|
|
289 bool HasDQI;
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290
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291 /// Processor has AVX-512 Byte and Word instructions
|
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292 bool HasBWI;
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293
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294 /// Processor has AVX-512 Vector Length eXtenstions
|
|
|
295 bool HasVLX;
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|
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296
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100
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297 /// Processor has PKU extenstions
|
|
|
298 bool HasPKU;
|
|
|
299
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|
|
300 /// Processor supports MPX - Memory Protection Extensions
|
|
95
|
301 bool HasMPX;
|
|
|
302
|
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100
|
303 /// Processor has Software Guard Extensions
|
|
|
304 bool HasSGX;
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|
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305
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|
|
306 /// Processor supports Flush Cache Line instruction
|
|
|
307 bool HasCLFLUSHOPT;
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|
308
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|
|
309 /// Processor supports Cache Line Write Back instruction
|
|
|
310 bool HasCLWB;
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|
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311
|
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95
|
312 /// Use software floating point for code generation.
|
|
|
313 bool UseSoftFloat;
|
|
|
314
|
|
83
|
315 /// The minimum alignment known to hold of the stack frame on
|
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316 /// entry to the function and which must be maintained by every function.
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317 unsigned stackAlignment;
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318
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319 /// Max. memset / memcpy size that is turned into rep/movs, rep/stos ops.
|
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320 ///
|
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321 unsigned MaxInlineSizeThreshold;
|
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322
|
|
83
|
323 /// What processor and OS we're targeting.
|
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324 Triple TargetTriple;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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|
325
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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|
326 /// Instruction itineraries for scheduling
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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327 InstrItineraryData InstrItins;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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328
|
|
121
|
329 /// GlobalISel related APIs.
|
|
|
330 std::unique_ptr<CallLowering> CallLoweringInfo;
|
|
|
331 std::unique_ptr<LegalizerInfo> Legalizer;
|
|
|
332 std::unique_ptr<RegisterBankInfo> RegBankInfo;
|
|
|
333 std::unique_ptr<InstructionSelector> InstSelector;
|
|
|
334
|
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335 private:
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|
83
|
336 /// Override the stack alignment.
|
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|
337 unsigned StackAlignOverride;
|
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|
338
|
|
83
|
339 /// True if compiling for 64-bit, false for 16-bit or 32-bit.
|
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340 bool In64BitMode;
|
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|
341
|
|
83
|
342 /// True if compiling for 32-bit, false for 16-bit or 64-bit.
|
|
77
|
343 bool In32BitMode;
|
|
|
344
|
|
83
|
345 /// True if compiling for 16-bit, false for 32-bit or 64-bit.
|
|
77
|
346 bool In16BitMode;
|
|
|
347
|
|
121
|
348 /// Contains the Overhead of gather\scatter instructions
|
|
|
349 int GatherOverhead;
|
|
|
350 int ScatterOverhead;
|
|
|
351
|
|
77
|
352 X86SelectionDAGInfo TSInfo;
|
|
|
353 // Ordering here is important. X86InstrInfo initializes X86RegisterInfo which
|
|
|
354 // X86TargetLowering needs.
|
|
|
355 X86InstrInfo InstrInfo;
|
|
|
356 X86TargetLowering TLInfo;
|
|
|
357 X86FrameLowering FrameLowering;
|
|
|
358
|
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|
359 public:
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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|
360 /// This constructor initializes the data members to match that
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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diff
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|
361 /// of the specified triple.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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|
362 ///
|
|
120
|
363 X86Subtarget(const Triple &TT, StringRef CPU, StringRef FS,
|
|
95
|
364 const X86TargetMachine &TM, unsigned StackAlignOverride);
|
|
77
|
365
|
|
|
366 const X86TargetLowering *getTargetLowering() const override {
|
|
|
367 return &TLInfo;
|
|
|
368 }
|
|
121
|
369
|
|
77
|
370 const X86InstrInfo *getInstrInfo() const override { return &InstrInfo; }
|
|
121
|
371
|
|
77
|
372 const X86FrameLowering *getFrameLowering() const override {
|
|
|
373 return &FrameLowering;
|
|
|
374 }
|
|
121
|
375
|
|
77
|
376 const X86SelectionDAGInfo *getSelectionDAGInfo() const override {
|
|
|
377 return &TSInfo;
|
|
|
378 }
|
|
121
|
379
|
|
77
|
380 const X86RegisterInfo *getRegisterInfo() const override {
|
|
|
381 return &getInstrInfo()->getRegisterInfo();
|
|
|
382 }
|
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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|
383
|
|
83
|
384 /// Returns the minimum alignment known to hold of the
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
385 /// stack frame on entry to the function and which must be maintained by every
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
386 /// function for this subtarget.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
387 unsigned getStackAlignment() const { return stackAlignment; }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
388
|
|
83
|
389 /// Returns the maximum memset / memcpy size
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
390 /// that still makes it profitable to inline the call.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
391 unsigned getMaxInlineSizeThreshold() const { return MaxInlineSizeThreshold; }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
392
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
393 /// ParseSubtargetFeatures - Parses features string setting specified
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
394 /// subtarget options. Definition of function is auto generated by tblgen.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
395 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
396
|
|
120
|
397 /// Methods used by Global ISel
|
|
|
398 const CallLowering *getCallLowering() const override;
|
|
|
399 const InstructionSelector *getInstructionSelector() const override;
|
|
|
400 const LegalizerInfo *getLegalizerInfo() const override;
|
|
|
401 const RegisterBankInfo *getRegBankInfo() const override;
|
|
121
|
402
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
403 private:
|
|
83
|
404 /// Initialize the full set of dependencies so we can use an initializer
|
|
77
|
405 /// list for X86Subtarget.
|
|
|
406 X86Subtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
407 void initializeEnvironment();
|
|
77
|
408 void initSubtargetFeatures(StringRef CPU, StringRef FS);
|
|
121
|
409
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
410 public:
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
411 /// Is this x86_64? (disregarding specific ABI / programming model)
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
412 bool is64Bit() const {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
413 return In64BitMode;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
414 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
415
|
|
77
|
416 bool is32Bit() const {
|
|
|
417 return In32BitMode;
|
|
|
418 }
|
|
|
419
|
|
|
420 bool is16Bit() const {
|
|
|
421 return In16BitMode;
|
|
|
422 }
|
|
|
423
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
424 /// Is this x86_64 with the ILP32 programming model (x32 ABI)?
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
425 bool isTarget64BitILP32() const {
|
|
77
|
426 return In64BitMode && (TargetTriple.getEnvironment() == Triple::GNUX32 ||
|
|
83
|
427 TargetTriple.isOSNaCl());
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
428 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
429
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
430 /// Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
431 bool isTarget64BitLP64() const {
|
|
77
|
432 return In64BitMode && (TargetTriple.getEnvironment() != Triple::GNUX32 &&
|
|
83
|
433 !TargetTriple.isOSNaCl());
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
434 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
435
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
436 PICStyles::Style getPICStyle() const { return PICStyle; }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
437 void setPICStyle(PICStyles::Style Style) { PICStyle = Style; }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
438
|
|
120
|
439 bool hasX87() const { return HasX87; }
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
440 bool hasCMov() const { return HasCMov; }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
441 bool hasSSE1() const { return X86SSELevel >= SSE1; }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
442 bool hasSSE2() const { return X86SSELevel >= SSE2; }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
443 bool hasSSE3() const { return X86SSELevel >= SSE3; }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
444 bool hasSSSE3() const { return X86SSELevel >= SSSE3; }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
445 bool hasSSE41() const { return X86SSELevel >= SSE41; }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
446 bool hasSSE42() const { return X86SSELevel >= SSE42; }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
447 bool hasAVX() const { return X86SSELevel >= AVX; }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
448 bool hasAVX2() const { return X86SSELevel >= AVX2; }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
449 bool hasAVX512() const { return X86SSELevel >= AVX512F; }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
450 bool hasFp256() const { return hasAVX(); }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
451 bool hasInt256() const { return hasAVX2(); }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
452 bool hasSSE4A() const { return HasSSE4A; }
|
|
100
|
453 bool hasMMX() const { return X863DNowLevel >= MMX; }
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
454 bool has3DNow() const { return X863DNowLevel >= ThreeDNow; }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
455 bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
456 bool hasPOPCNT() const { return HasPOPCNT; }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
457 bool hasAES() const { return HasAES; }
|
|
100
|
458 bool hasFXSR() const { return HasFXSR; }
|
|
95
|
459 bool hasXSAVE() const { return HasXSAVE; }
|
|
|
460 bool hasXSAVEOPT() const { return HasXSAVEOPT; }
|
|
|
461 bool hasXSAVEC() const { return HasXSAVEC; }
|
|
|
462 bool hasXSAVES() const { return HasXSAVES; }
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
463 bool hasPCLMUL() const { return HasPCLMUL; }
|
|
100
|
464 // Prefer FMA4 to FMA - its better for commutation/memory folding and
|
|
|
465 // has equal or better performance on all supported targets.
|
|
121
|
466 bool hasFMA() const { return (HasFMA || hasAVX512()) && !HasFMA4; }
|
|
100
|
467 bool hasFMA4() const { return HasFMA4; }
|
|
121
|
468 bool hasAnyFMA() const { return hasFMA() || hasFMA4(); }
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
469 bool hasXOP() const { return HasXOP; }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
470 bool hasTBM() const { return HasTBM; }
|
|
121
|
471 bool hasLWP() const { return HasLWP; }
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
472 bool hasMOVBE() const { return HasMOVBE; }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
473 bool hasRDRAND() const { return HasRDRAND; }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
474 bool hasF16C() const { return HasF16C; }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
475 bool hasFSGSBase() const { return HasFSGSBase; }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
476 bool hasLZCNT() const { return HasLZCNT; }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
477 bool hasBMI() const { return HasBMI; }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
478 bool hasBMI2() const { return HasBMI2; }
|
|
100
|
479 bool hasVBMI() const { return HasVBMI; }
|
|
|
480 bool hasIFMA() const { return HasIFMA; }
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
481 bool hasRTM() const { return HasRTM; }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
482 bool hasADX() const { return HasADX; }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
483 bool hasSHA() const { return HasSHA; }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
484 bool hasPRFCHW() const { return HasPRFCHW; }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
485 bool hasRDSEED() const { return HasRDSEED; }
|
|
100
|
486 bool hasLAHFSAHF() const { return HasLAHFSAHF; }
|
|
120
|
487 bool hasMWAITX() const { return HasMWAITX; }
|
|
121
|
488 bool hasCLZERO() const { return HasCLZERO; }
|
|
33
|
489 bool isSHLDSlow() const { return IsSHLDSlow; }
|
|
121
|
490 bool isPMULLDSlow() const { return IsPMULLDSlow; }
|
|
95
|
491 bool isUnalignedMem16Slow() const { return IsUAMem16Slow; }
|
|
83
|
492 bool isUnalignedMem32Slow() const { return IsUAMem32Slow; }
|
|
121
|
493 int getGatherOverhead() const { return GatherOverhead; }
|
|
|
494 int getScatterOverhead() const { return ScatterOverhead; }
|
|
83
|
495 bool hasSSEUnalignedMem() const { return HasSSEUnalignedMem; }
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
496 bool hasCmpxchg16b() const { return HasCmpxchg16b; }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
497 bool useLeaForSP() const { return UseLeaForSP; }
|
|
121
|
498 bool hasFastPartialYMMorZMMWrite() const {
|
|
|
499 return HasFastPartialYMMorZMMWrite;
|
|
|
500 }
|
|
120
|
501 bool hasFastScalarFSQRT() const { return HasFastScalarFSQRT; }
|
|
|
502 bool hasFastVectorFSQRT() const { return HasFastVectorFSQRT; }
|
|
|
503 bool hasFastLZCNT() const { return HasFastLZCNT; }
|
|
121
|
504 bool hasFastSHLDRotate() const { return HasFastSHLDRotate; }
|
|
|
505 bool hasMacroFusion() const { return HasMacroFusion; }
|
|
|
506 bool hasERMSB() const { return HasERMSB; }
|
|
83
|
507 bool hasSlowDivide32() const { return HasSlowDivide32; }
|
|
|
508 bool hasSlowDivide64() const { return HasSlowDivide64; }
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
509 bool padShortFunctions() const { return PadShortFunctions; }
|
|
121
|
510 bool slowTwoMemOps() const { return SlowTwoMemOps; }
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
511 bool LEAusesAG() const { return LEAUsesAG; }
|
|
77
|
512 bool slowLEA() const { return SlowLEA; }
|
|
121
|
513 bool slow3OpsLEA() const { return Slow3OpsLEA; }
|
|
77
|
514 bool slowIncDec() const { return SlowIncDec; }
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
515 bool hasCDI() const { return HasCDI; }
|
|
121
|
516 bool hasVPOPCNTDQ() const { return HasVPOPCNTDQ; }
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
517 bool hasPFI() const { return HasPFI; }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
518 bool hasERI() const { return HasERI; }
|
|
77
|
519 bool hasDQI() const { return HasDQI; }
|
|
|
520 bool hasBWI() const { return HasBWI; }
|
|
|
521 bool hasVLX() const { return HasVLX; }
|
|
100
|
522 bool hasPKU() const { return HasPKU; }
|
|
95
|
523 bool hasMPX() const { return HasMPX; }
|
|
121
|
524 bool hasCLFLUSHOPT() const { return HasCLFLUSHOPT; }
|
|
|
525 bool hasCLWB() const { return HasCLWB; }
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
526
|
|
121
|
527 bool isXRaySupported() const override { return is64Bit(); }
|
|
120
|
528
|
|
121
|
529 X86ProcFamilyEnum getProcFamily() const { return X86ProcFamily; }
|
|
|
530
|
|
|
531 /// TODO: to be removed later and replaced with suitable properties
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
532 bool isAtom() const { return X86ProcFamily == IntelAtom; }
|
|
77
|
533 bool isSLM() const { return X86ProcFamily == IntelSLM; }
|
|
95
|
534 bool useSoftFloat() const { return UseSoftFloat; }
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
535
|
|
120
|
536 /// Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
|
|
|
537 /// no-sse2). There isn't any reason to disable it if the target processor
|
|
|
538 /// supports it.
|
|
|
539 bool hasMFence() const { return hasSSE2() || is64Bit(); }
|
|
|
540
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
541 const Triple &getTargetTriple() const { return TargetTriple; }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
542
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
543 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
|
|
83
|
544 bool isTargetFreeBSD() const { return TargetTriple.isOSFreeBSD(); }
|
|
|
545 bool isTargetDragonFly() const { return TargetTriple.isOSDragonFly(); }
|
|
|
546 bool isTargetSolaris() const { return TargetTriple.isOSSolaris(); }
|
|
121
|
547 bool isTargetPS4() const { return TargetTriple.isPS4CPU(); }
|
|
33
|
548
|
|
|
549 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
|
|
|
550 bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
|
|
83
|
551 bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
|
|
33
|
552
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
553 bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
|
|
120
|
554 bool isTargetKFreeBSD() const { return TargetTriple.isOSKFreeBSD(); }
|
|
|
555 bool isTargetGlibc() const { return TargetTriple.isOSGlibc(); }
|
|
95
|
556 bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
557 bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
558 bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
559 bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); }
|
|
100
|
560 bool isTargetMCU() const { return TargetTriple.isOSIAMCU(); }
|
|
121
|
561 bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); }
|
|
77
|
562
|
|
|
563 bool isTargetWindowsMSVC() const {
|
|
|
564 return TargetTriple.isWindowsMSVCEnvironment();
|
|
|
565 }
|
|
|
566
|
|
|
567 bool isTargetKnownWindowsMSVC() const {
|
|
|
568 return TargetTriple.isKnownWindowsMSVCEnvironment();
|
|
|
569 }
|
|
|
570
|
|
95
|
571 bool isTargetWindowsCoreCLR() const {
|
|
|
572 return TargetTriple.isWindowsCoreCLREnvironment();
|
|
|
573 }
|
|
|
574
|
|
77
|
575 bool isTargetWindowsCygwin() const {
|
|
|
576 return TargetTriple.isWindowsCygwinEnvironment();
|
|
|
577 }
|
|
|
578
|
|
|
579 bool isTargetWindowsGNU() const {
|
|
|
580 return TargetTriple.isWindowsGNUEnvironment();
|
|
|
581 }
|
|
|
582
|
|
83
|
583 bool isTargetWindowsItanium() const {
|
|
|
584 return TargetTriple.isWindowsItaniumEnvironment();
|
|
|
585 }
|
|
|
586
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
587 bool isTargetCygMing() const { return TargetTriple.isOSCygMing(); }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
588
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
589 bool isOSWindows() const { return TargetTriple.isOSWindows(); }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
590
|
|
121
|
591 bool isTargetWin64() const { return In64BitMode && isOSWindows(); }
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
592
|
|
121
|
593 bool isTargetWin32() const { return !In64BitMode && isOSWindows(); }
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
594
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
595 bool isPICStyleGOT() const { return PICStyle == PICStyles::GOT; }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
596 bool isPICStyleRIPRel() const { return PICStyle == PICStyles::RIPRel; }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
597
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
598 bool isPICStyleStubPIC() const {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
599 return PICStyle == PICStyles::StubPIC;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
600 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
601
|
|
120
|
602 bool isPositionIndependent() const { return TM.isPositionIndependent(); }
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
603
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
604 bool isCallingConvWin64(CallingConv::ID CC) const {
|
|
95
|
605 switch (CC) {
|
|
|
606 // On Win64, all these conventions just use the default convention.
|
|
|
607 case CallingConv::C:
|
|
|
608 case CallingConv::Fast:
|
|
121
|
609 case CallingConv::Swift:
|
|
95
|
610 case CallingConv::X86_FastCall:
|
|
|
611 case CallingConv::X86_StdCall:
|
|
|
612 case CallingConv::X86_ThisCall:
|
|
|
613 case CallingConv::X86_VectorCall:
|
|
|
614 case CallingConv::Intel_OCL_BI:
|
|
|
615 return isTargetWin64();
|
|
|
616 // This convention allows using the Win64 convention on other targets.
|
|
121
|
617 case CallingConv::Win64:
|
|
95
|
618 return true;
|
|
|
619 // This convention allows using the SysV convention on Windows targets.
|
|
|
620 case CallingConv::X86_64_SysV:
|
|
|
621 return false;
|
|
|
622 // Otherwise, who knows what this is.
|
|
|
623 default:
|
|
|
624 return false;
|
|
|
625 }
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
626 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
627
|
|
120
|
628 /// Classify a global variable reference for the current subtarget according
|
|
|
629 /// to how we should reference it in a non-pcrel context.
|
|
|
630 unsigned char classifyLocalReference(const GlobalValue *GV) const;
|
|
|
631
|
|
|
632 unsigned char classifyGlobalReference(const GlobalValue *GV,
|
|
|
633 const Module &M) const;
|
|
|
634 unsigned char classifyGlobalReference(const GlobalValue *GV) const;
|
|
|
635
|
|
|
636 /// Classify a global function reference for the current subtarget.
|
|
|
637 unsigned char classifyGlobalFunctionReference(const GlobalValue *GV,
|
|
|
638 const Module &M) const;
|
|
|
639 unsigned char classifyGlobalFunctionReference(const GlobalValue *GV) const;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
640
|
|
83
|
641 /// Classify a blockaddress reference for the current subtarget according to
|
|
|
642 /// how we should reference it in a non-pcrel context.
|
|
120
|
643 unsigned char classifyBlockAddressReference() const;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
644
|
|
83
|
645 /// Return true if the subtarget allows calls to immediate address.
|
|
120
|
646 bool isLegalToCallImmediateAddr() const;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
647
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
648 /// This function returns the name of a function which has an interface
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
649 /// like the non-standard bzero function, if such a function exists on
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
650 /// the current subtarget and it is considered prefereable over
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
651 /// memset with zero passed as the second argument. Otherwise it
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
652 /// returns null.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
653 const char *getBZeroEntry() const;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
654
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
655 /// This function returns true if the target has sincos() routine in its
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
656 /// compiler runtime or math libraries.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
657 bool hasSinCos() const;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
658
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
659 /// Enable the MachineScheduler pass for all X86 subtargets.
|
|
77
|
660 bool enableMachineScheduler() const override { return true; }
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
661
|
|
121
|
662 // TODO: Update the regression tests and return true.
|
|
|
663 bool supportPrintSchedInfo() const override { return false; }
|
|
|
664
|
|
77
|
665 bool enableEarlyIfConversion() const override;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
666
|
|
83
|
667 /// Return the instruction itineraries based on the subtarget selection.
|
|
77
|
668 const InstrItineraryData *getInstrItineraryData() const override {
|
|
|
669 return &InstrItins;
|
|
|
670 }
|
|
|
671
|
|
|
672 AntiDepBreakMode getAntiDepBreakMode() const override {
|
|
|
673 return TargetSubtargetInfo::ANTIDEP_CRITICAL;
|
|
|
674 }
|
|
121
|
675
|
|
|
676 bool enableAdvancedRASplitCost() const override { return true; }
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
677 };
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
678
|
|
121
|
679 } // end namespace llvm
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
680
|
|
121
|
681 #endif // LLVM_LIB_TARGET_X86_X86SUBTARGET_H
|
