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annotate test/CodeGen/AArch64/arm64-zextload-unscaled.ll @ 128:c347d3398279 default tip

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fix
author mir3636
date Wed, 06 Dec 2017 14:37:17 +0900
parents 1172e4bd9c6f
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
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1172e4bd9c6f update 4.0.0
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1 ; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
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3 @var32 = global i32 0
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5 define void @test_zextloadi1_unscaled(i1* %base) {
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6 ; CHECK-LABEL: test_zextloadi1_unscaled:
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7 ; CHECK: ldurb {{w[0-9]+}}, [{{x[0-9]+}}, #-7]
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9 %addr = getelementptr i1, i1* %base, i32 -7
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10 %val = load i1, i1* %addr, align 1
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12 %extended = zext i1 %val to i32
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13 store i32 %extended, i32* @var32, align 4
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14 ret void
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15 }
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16
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17 define void @test_zextloadi8_unscaled(i8* %base) {
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18 ; CHECK-LABEL: test_zextloadi8_unscaled:
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19 ; CHECK: ldurb {{w[0-9]+}}, [{{x[0-9]+}}, #-7]
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20
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21 %addr = getelementptr i8, i8* %base, i32 -7
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22 %val = load i8, i8* %addr, align 1
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24 %extended = zext i8 %val to i32
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25 store i32 %extended, i32* @var32, align 4
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26 ret void
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27 }
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29 define void @test_zextloadi16_unscaled(i16* %base) {
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30 ; CHECK-LABEL: test_zextloadi16_unscaled:
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31 ; CHECK: ldurh {{w[0-9]+}}, [{{x[0-9]+}}, #-14]
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32
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33 %addr = getelementptr i16, i16* %base, i32 -7
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34 %val = load i16, i16* %addr, align 2
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36 %extended = zext i16 %val to i32
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37 store i32 %extended, i32* @var32, align 4
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38 ret void
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39 }
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