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annotate test/CodeGen/AMDGPU/add_i64.ll @ 128:c347d3398279 default tip

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fix
author mir3636
date Wed, 06 Dec 2017 14:37:17 +0900
parents 803732b1fca8
children
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1 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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2
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4 declare i32 @llvm.amdgcn.workitem.id.x() readnone
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5
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6 ; SI-LABEL: {{^}}test_i64_vreg:
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7 ; SI: v_add_i32
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8 ; SI: v_addc_u32
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9 define amdgpu_kernel void @test_i64_vreg(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %inA, i64 addrspace(1)* noalias %inB) {
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10 %tid = call i32 @llvm.amdgcn.workitem.id.x() readnone
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11 %a_ptr = getelementptr i64, i64 addrspace(1)* %inA, i32 %tid
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12 %b_ptr = getelementptr i64, i64 addrspace(1)* %inB, i32 %tid
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13 %a = load i64, i64 addrspace(1)* %a_ptr
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14 %b = load i64, i64 addrspace(1)* %b_ptr
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15 %result = add i64 %a, %b
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16 store i64 %result, i64 addrspace(1)* %out
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17 ret void
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18 }
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19
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20 ; Check that the SGPR add operand is correctly moved to a VGPR.
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21 ; SI-LABEL: {{^}}sgpr_operand:
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22 ; SI: s_add_u32
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23 ; SI: s_addc_u32
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24 define amdgpu_kernel void @sgpr_operand(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in, i64 addrspace(1)* noalias %in_bar, i64 %a) {
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25 %foo = load i64, i64 addrspace(1)* %in, align 8
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26 %result = add i64 %foo, %a
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27 store i64 %result, i64 addrspace(1)* %out
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28 ret void
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29 }
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31 ; Swap the arguments. Check that the SGPR -> VGPR copy works with the
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32 ; SGPR as other operand.
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33 ;
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34 ; SI-LABEL: {{^}}sgpr_operand_reversed:
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35 ; SI: s_add_u32
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36 ; SI: s_addc_u32
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37 define amdgpu_kernel void @sgpr_operand_reversed(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in, i64 %a) {
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38 %foo = load i64, i64 addrspace(1)* %in, align 8
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39 %result = add i64 %a, %foo
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40 store i64 %result, i64 addrspace(1)* %out
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41 ret void
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42 }
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45 ; SI-LABEL: {{^}}test_v2i64_sreg:
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46 ; SI: s_add_u32
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47 ; SI: s_addc_u32
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48 ; SI: s_add_u32
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49 ; SI: s_addc_u32
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50 define amdgpu_kernel void @test_v2i64_sreg(<2 x i64> addrspace(1)* noalias %out, <2 x i64> %a, <2 x i64> %b) {
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51 %result = add <2 x i64> %a, %b
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52 store <2 x i64> %result, <2 x i64> addrspace(1)* %out
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53 ret void
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54 }
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56 ; SI-LABEL: {{^}}test_v2i64_vreg:
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57 ; SI: v_add_i32
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58 ; SI: v_addc_u32
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59 ; SI: v_add_i32
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60 ; SI: v_addc_u32
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61 define amdgpu_kernel void @test_v2i64_vreg(<2 x i64> addrspace(1)* noalias %out, <2 x i64> addrspace(1)* noalias %inA, <2 x i64> addrspace(1)* noalias %inB) {
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62 %tid = call i32 @llvm.amdgcn.workitem.id.x() readnone
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63 %a_ptr = getelementptr <2 x i64>, <2 x i64> addrspace(1)* %inA, i32 %tid
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64 %b_ptr = getelementptr <2 x i64>, <2 x i64> addrspace(1)* %inB, i32 %tid
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65 %a = load <2 x i64>, <2 x i64> addrspace(1)* %a_ptr
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66 %b = load <2 x i64>, <2 x i64> addrspace(1)* %b_ptr
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67 %result = add <2 x i64> %a, %b
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68 store <2 x i64> %result, <2 x i64> addrspace(1)* %out
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69 ret void
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70 }
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71
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72 ; SI-LABEL: {{^}}trunc_i64_add_to_i32:
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73 ; SI: s_load_dword s[[SREG0:[0-9]+]]
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74 ; SI: s_load_dword s[[SREG1:[0-9]+]]
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75 ; SI: s_add_i32 [[SRESULT:s[0-9]+]], s[[SREG1]], s[[SREG0]]
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76 ; SI-NOT: addc
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77 ; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[SRESULT]]
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78 ; SI: buffer_store_dword [[VRESULT]],
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79 define amdgpu_kernel void @trunc_i64_add_to_i32(i32 addrspace(1)* %out, i64 %a, i64 %b) {
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80 %add = add i64 %b, %a
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81 %trunc = trunc i64 %add to i32
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82 store i32 %trunc, i32 addrspace(1)* %out, align 8
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83 ret void
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84 }