annotate test/CodeGen/AMDGPU/build_vector.ll @ 128:c347d3398279 default tip

fix
author mir3636
date Wed, 06 Dec 2017 14:37:17 +0900
parents 803732b1fca8
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
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60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 0
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1 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600
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2 ; RUN: llc < %s -march=amdgcn -verify-machineinstrs | FileCheck %s --check-prefix=SI
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3 ; RUN: llc < %s -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s --check-prefix=SI
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95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 0
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5 ; R600: {{^}}build_vector2:
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 0
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6 ; R600: MOV
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 0
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7 ; R600: MOV
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Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 0
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8 ; R600-NOT: MOV
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 0
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9 ; SI: {{^}}build_vector2:
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 0
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10 ; SI-DAG: v_mov_b32_e32 v[[X:[0-9]]], 5
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 0
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11 ; SI-DAG: v_mov_b32_e32 v[[Y:[0-9]]], 6
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 0
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12 ; SI: buffer_store_dwordx2 v{{\[}}[[X]]:[[Y]]{{\]}}
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13 define amdgpu_kernel void @build_vector2 (<2 x i32> addrspace(1)* %out) {
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14 entry:
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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15 store <2 x i32> <i32 5, i32 6>, <2 x i32> addrspace(1)* %out
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16 ret void
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17 }
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60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 0
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19 ; R600: {{^}}build_vector4:
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 0
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20 ; R600: MOV
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 0
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21 ; R600: MOV
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 0
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22 ; R600: MOV
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 0
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23 ; R600: MOV
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Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 0
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24 ; R600-NOT: MOV
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Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 0
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25 ; SI: {{^}}build_vector4:
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Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 0
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26 ; SI-DAG: v_mov_b32_e32 v[[X:[0-9]]], 5
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 0
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27 ; SI-DAG: v_mov_b32_e32 v[[Y:[0-9]]], 6
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 0
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28 ; SI-DAG: v_mov_b32_e32 v[[Z:[0-9]]], 7
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 0
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29 ; SI-DAG: v_mov_b32_e32 v[[W:[0-9]]], 8
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 0
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30 ; SI: buffer_store_dwordx4 v{{\[}}[[X]]:[[W]]{{\]}}
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kono
parents: 95
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31 define amdgpu_kernel void @build_vector4 (<4 x i32> addrspace(1)* %out) {
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parents:
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32 entry:
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parents:
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33 store <4 x i32> <i32 5, i32 6, i32 7, i32 8>, <4 x i32> addrspace(1)* %out
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parents:
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34 ret void
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35 }