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121
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1 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC -check-prefix=GCN %s
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2 ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=FUNC -check-prefix=GCN %s
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3 ; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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4
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100
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5 declare i8 @llvm.ctlz.i8(i8, i1) nounwind readnone
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6
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7 declare i32 @llvm.ctlz.i32(i32, i1) nounwind readnone
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8 declare <2 x i32> @llvm.ctlz.v2i32(<2 x i32>, i1) nounwind readnone
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9 declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1) nounwind readnone
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10
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100
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11 declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone
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12 declare <2 x i64> @llvm.ctlz.v2i64(<2 x i64>, i1) nounwind readnone
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13 declare <4 x i64> @llvm.ctlz.v4i64(<4 x i64>, i1) nounwind readnone
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14
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15 declare i32 @llvm.r600.read.tidig.x() nounwind readnone
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16
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17 ; FUNC-LABEL: {{^}}s_ctlz_zero_undef_i32:
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120
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18 ; GCN: s_load_dword [[VAL:s[0-9]+]],
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19 ; GCN: s_flbit_i32_b32 [[SRESULT:s[0-9]+]], [[VAL]]
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20 ; GCN: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[SRESULT]]
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21 ; GCN: buffer_store_dword [[VRESULT]],
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22 ; GCN: s_endpgm
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23 ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+\.[XYZW]]]
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24 ; EG: FFBH_UINT {{\*? *}}[[RESULT]]
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121
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25 define amdgpu_kernel void @s_ctlz_zero_undef_i32(i32 addrspace(1)* noalias %out, i32 %val) nounwind {
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26 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 true) nounwind readnone
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27 store i32 %ctlz, i32 addrspace(1)* %out, align 4
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28 ret void
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29 }
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30
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31 ; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i32:
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121
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32 ; GCN: {{buffer|flat}}_load_dword [[VAL:v[0-9]+]],
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120
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33 ; GCN: v_ffbh_u32_e32 [[RESULT:v[0-9]+]], [[VAL]]
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34 ; GCN: buffer_store_dword [[RESULT]],
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35 ; GCN: s_endpgm
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36 ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+\.[XYZW]]]
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37 ; EG: FFBH_UINT {{\*? *}}[[RESULT]]
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121
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38 define amdgpu_kernel void @v_ctlz_zero_undef_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind {
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39 %tid = call i32 @llvm.r600.read.tidig.x()
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40 %in.gep = getelementptr i32, i32 addrspace(1)* %valptr, i32 %tid
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41 %val = load i32, i32 addrspace(1)* %in.gep, align 4
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42 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 true) nounwind readnone
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43 store i32 %ctlz, i32 addrspace(1)* %out, align 4
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44 ret void
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45 }
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46
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47 ; FUNC-LABEL: {{^}}v_ctlz_zero_undef_v2i32:
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121
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48 ; GCN: {{buffer|flat}}_load_dwordx2
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120
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49 ; GCN: v_ffbh_u32_e32
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50 ; GCN: v_ffbh_u32_e32
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51 ; GCN: buffer_store_dwordx2
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52 ; GCN: s_endpgm
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53 ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+]]{{\.[XYZW]}}
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54 ; EG: FFBH_UINT {{\*? *}}[[RESULT]]
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55 ; EG: FFBH_UINT {{\*? *}}[[RESULT]]
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121
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56 define amdgpu_kernel void @v_ctlz_zero_undef_v2i32(<2 x i32> addrspace(1)* noalias %out, <2 x i32> addrspace(1)* noalias %valptr) nounwind {
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57 %tid = call i32 @llvm.r600.read.tidig.x()
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58 %in.gep = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %valptr, i32 %tid
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59 %val = load <2 x i32>, <2 x i32> addrspace(1)* %in.gep, align 8
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60 %ctlz = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %val, i1 true) nounwind readnone
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61 store <2 x i32> %ctlz, <2 x i32> addrspace(1)* %out, align 8
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62 ret void
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63 }
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64
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65 ; FUNC-LABEL: {{^}}v_ctlz_zero_undef_v4i32:
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121
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66 ; GCN: {{buffer|flat}}_load_dwordx4
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120
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67 ; GCN: v_ffbh_u32_e32
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68 ; GCN: v_ffbh_u32_e32
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69 ; GCN: v_ffbh_u32_e32
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70 ; GCN: v_ffbh_u32_e32
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71 ; GCN: buffer_store_dwordx4
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72 ; GCN: s_endpgm
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73 ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+]]{{\.[XYZW]}}
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74 ; EG: FFBH_UINT {{\*? *}}[[RESULT]]
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75 ; EG: FFBH_UINT {{\*? *}}[[RESULT]]
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76 ; EG: FFBH_UINT {{\*? *}}[[RESULT]]
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77 ; EG: FFBH_UINT {{\*? *}}[[RESULT]]
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121
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78 define amdgpu_kernel void @v_ctlz_zero_undef_v4i32(<4 x i32> addrspace(1)* noalias %out, <4 x i32> addrspace(1)* noalias %valptr) nounwind {
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79 %tid = call i32 @llvm.r600.read.tidig.x()
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80 %in.gep = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %valptr, i32 %tid
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81 %val = load <4 x i32>, <4 x i32> addrspace(1)* %in.gep, align 16
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82 %ctlz = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %val, i1 true) nounwind readnone
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83 store <4 x i32> %ctlz, <4 x i32> addrspace(1)* %out, align 16
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84 ret void
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85 }
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100
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86
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87 ; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i8:
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121
|
88 ; GCN: {{buffer|flat}}_load_ubyte [[VAL:v[0-9]+]],
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120
|
89 ; GCN: v_ffbh_u32_e32 [[RESULT:v[0-9]+]], [[VAL]]
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90 ; GCN: buffer_store_byte [[RESULT]],
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121
|
91 define amdgpu_kernel void @v_ctlz_zero_undef_i8(i8 addrspace(1)* noalias %out, i8 addrspace(1)* noalias %valptr) nounwind {
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92 %tid = call i32 @llvm.r600.read.tidig.x()
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93 %in.gep = getelementptr i8, i8 addrspace(1)* %valptr, i32 %tid
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94 %val = load i8, i8 addrspace(1)* %in.gep
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100
|
95 %ctlz = call i8 @llvm.ctlz.i8(i8 %val, i1 true) nounwind readnone
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|
96 store i8 %ctlz, i8 addrspace(1)* %out
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|
97 ret void
|
|
|
98 }
|
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|
99
|
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100 ; FUNC-LABEL: {{^}}s_ctlz_zero_undef_i64:
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120
|
101 ; GCN: s_load_dwordx2 s{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0xb|0x2c}}
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102 ; GCN-DAG: v_cmp_eq_u32_e64 vcc, s[[HI]], 0{{$}}
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103 ; GCN-DAG: s_flbit_i32_b32 [[FFBH_LO:s[0-9]+]], s[[LO]]
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104 ; GCN-DAG: s_add_i32 [[ADD:s[0-9]+]], [[FFBH_LO]], 32
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105 ; GCN-DAG: s_flbit_i32_b32 [[FFBH_HI:s[0-9]+]], s[[HI]]
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106 ; GCN-DAG: v_mov_b32_e32 [[VFFBH_LO:v[0-9]+]], [[FFBH_LO]]
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107 ; GCN-DAG: v_mov_b32_e32 [[VFFBH_HI:v[0-9]+]], [[FFBH_HI]]
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108 ; GCN-DAG: v_cndmask_b32_e32 v[[CTLZ:[0-9]+]], [[VFFBH_HI]], [[VFFBH_LO]]
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109 ; GCN-DAG: v_mov_b32_e32 v[[CTLZ_HI:[0-9]+]], 0{{$}}
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110 ; GCN: {{buffer|flat}}_store_dwordx2 v{{\[}}[[CTLZ]]:[[CTLZ_HI]]{{\]}}
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121
|
111 define amdgpu_kernel void @s_ctlz_zero_undef_i64(i64 addrspace(1)* noalias %out, i64 %val) nounwind {
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100
|
112 %ctlz = call i64 @llvm.ctlz.i64(i64 %val, i1 true)
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113 store i64 %ctlz, i64 addrspace(1)* %out
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|
114 ret void
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|
115 }
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116
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117 ; FUNC-LABEL: {{^}}s_ctlz_zero_undef_i64_trunc:
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121
|
118 define amdgpu_kernel void @s_ctlz_zero_undef_i64_trunc(i32 addrspace(1)* noalias %out, i64 %val) nounwind {
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100
|
119 %ctlz = call i64 @llvm.ctlz.i64(i64 %val, i1 true)
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120 %trunc = trunc i64 %ctlz to i32
|
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|
121 store i32 %trunc, i32 addrspace(1)* %out
|
|
|
122 ret void
|
|
|
123 }
|
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|
124
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|
|
125 ; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i64:
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120
|
126 ; GCN-DAG: {{buffer|flat}}_load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}
|
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121
|
127 ; GCN-DAG: v_cmp_eq_u32_e32 vcc, 0, v[[HI]]
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120
|
128 ; GCN-DAG: v_ffbh_u32_e32 [[FFBH_LO:v[0-9]+]], v[[LO]]
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129 ; GCN-DAG: v_add_i32_e32 [[ADD:v[0-9]+]], vcc, 32, [[FFBH_LO]]
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130 ; GCN-DAG: v_ffbh_u32_e32 [[FFBH_HI:v[0-9]+]], v[[HI]]
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121
|
131 ; GCN-DAG: v_cndmask_b32_e32 v[[CTLZ:[0-9]+]], [[FFBH_HI]], [[FFBH_LO]]
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132 ; GCN: {{buffer|flat}}_store_dwordx2 {{.*}}v{{\[}}[[CTLZ]]:[[CTLZ_HI:[0-9]+]]{{\]}}
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133 define amdgpu_kernel void @v_ctlz_zero_undef_i64(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in) nounwind {
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100
|
134 %tid = call i32 @llvm.r600.read.tidig.x()
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135 %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
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136 %out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %tid
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137 %val = load i64, i64 addrspace(1)* %in.gep
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|
138 %ctlz = call i64 @llvm.ctlz.i64(i64 %val, i1 true)
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|
139 store i64 %ctlz, i64 addrspace(1)* %out.gep
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|
140 ret void
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|
|
141 }
|
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142
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|
143 ; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i64_trunc:
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121
|
144 define amdgpu_kernel void @v_ctlz_zero_undef_i64_trunc(i32 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in) nounwind {
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100
|
145 %tid = call i32 @llvm.r600.read.tidig.x()
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|
146 %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
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147 %out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
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148 %val = load i64, i64 addrspace(1)* %in.gep
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|
149 %ctlz = call i64 @llvm.ctlz.i64(i64 %val, i1 true)
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|
150 %trunc = trunc i64 %ctlz to i32
|
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|
151 store i32 %trunc, i32 addrspace(1)* %out.gep
|
|
|
152 ret void
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|
|
153 }
|
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154
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155 ; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i32_sel_eq_neg1:
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121
|
156 ; GCN: {{buffer|flat}}_load_dword [[VAL:v[0-9]+]],
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120
|
157 ; GCN: v_ffbh_u32_e32 [[RESULT:v[0-9]+]], [[VAL]]
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158 ; GCN: buffer_store_dword [[RESULT]],
|
|
121
|
159 define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_eq_neg1(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind {
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160 %tid = call i32 @llvm.r600.read.tidig.x()
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|
161 %in.gep = getelementptr i32, i32 addrspace(1)* %valptr, i32 %tid
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|
162 %val = load i32, i32 addrspace(1)* %in.gep
|
|
100
|
163 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 true) nounwind readnone
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|
164 %cmp = icmp eq i32 %val, 0
|
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|
165 %sel = select i1 %cmp, i32 -1, i32 %ctlz
|
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|
166 store i32 %sel, i32 addrspace(1)* %out
|
|
|
167 ret void
|
|
|
168 }
|
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169
|
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170 ; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i32_sel_ne_neg1:
|
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121
|
171 ; GCN: {{buffer|flat}}_load_dword [[VAL:v[0-9]+]],
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120
|
172 ; GCN: v_ffbh_u32_e32 [[RESULT:v[0-9]+]], [[VAL]]
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173 ; GCN: buffer_store_dword [[RESULT]],
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|
121
|
174 define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_ne_neg1(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind {
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|
175 %tid = call i32 @llvm.r600.read.tidig.x()
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|
176 %in.gep = getelementptr i32, i32 addrspace(1)* %valptr, i32 %tid
|
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|
177 %val = load i32, i32 addrspace(1)* %in.gep
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|
100
|
178 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 true) nounwind readnone
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|
179 %cmp = icmp ne i32 %val, 0
|
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|
180 %sel = select i1 %cmp, i32 %ctlz, i32 -1
|
|
|
181 store i32 %sel, i32 addrspace(1)* %out
|
|
|
182 ret void
|
|
|
183 }
|
|
|
184
|
|
|
185 ; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i8_sel_eq_neg1:
|
|
120
|
186 ; GCN: {{buffer|flat}}_load_ubyte [[VAL:v[0-9]+]],
|
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|
187 ; GCN: v_ffbh_u32_e32 [[FFBH:v[0-9]+]], [[VAL]]
|
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|
188 ; GCN: {{buffer|flat}}_store_byte [[FFBH]],
|
|
121
|
189 define amdgpu_kernel void @v_ctlz_zero_undef_i8_sel_eq_neg1(i8 addrspace(1)* noalias %out, i8 addrspace(1)* noalias %valptr) nounwind {
|
|
120
|
190 %tid = call i32 @llvm.r600.read.tidig.x()
|
|
|
191 %valptr.gep = getelementptr i8, i8 addrspace(1)* %valptr, i32 %tid
|
|
|
192 %val = load i8, i8 addrspace(1)* %valptr.gep
|
|
100
|
193 %ctlz = call i8 @llvm.ctlz.i8(i8 %val, i1 true) nounwind readnone
|
|
|
194 %cmp = icmp eq i8 %val, 0
|
|
|
195 %sel = select i1 %cmp, i8 -1, i8 %ctlz
|
|
|
196 store i8 %sel, i8 addrspace(1)* %out
|
|
|
197 ret void
|
|
|
198 }
|
|
|
199
|
|
|
200 ; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i32_sel_eq_neg1_two_use:
|
|
121
|
201 ; GCN: {{buffer|flat}}_load_dword [[VAL:v[0-9]+]],
|
|
120
|
202 ; GCN-DAG: v_ffbh_u32_e32 [[RESULT0:v[0-9]+]], [[VAL]]
|
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203 ; GCN-DAG: v_cmp_eq_u32_e32 vcc, 0, [[VAL]]
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204 ; GCN-DAG: v_cndmask_b32_e64 [[RESULT1:v[0-9]+]], 0, 1, vcc
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205 ; GCN-DAG: buffer_store_dword [[RESULT0]]
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206 ; GCN-DAG: buffer_store_byte [[RESULT1]]
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207 ; GCN: s_endpgm
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121
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208 define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_eq_neg1_two_use(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind {
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209 %tid = call i32 @llvm.r600.read.tidig.x()
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210 %in.gep = getelementptr i32, i32 addrspace(1)* %valptr, i32 %tid
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211 %val = load i32, i32 addrspace(1)* %in.gep
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100
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212 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 true) nounwind readnone
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213 %cmp = icmp eq i32 %val, 0
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214 %sel = select i1 %cmp, i32 -1, i32 %ctlz
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215 store volatile i32 %sel, i32 addrspace(1)* %out
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216 store volatile i1 %cmp, i1 addrspace(1)* undef
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217 ret void
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218 }
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219
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220 ; Selected on wrong constant
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221 ; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i32_sel_eq_0:
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121
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222 ; GCN: {{buffer|flat}}_load_dword
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120
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223 ; GCN: v_ffbh_u32_e32
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224 ; GCN: v_cmp
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225 ; GCN: v_cndmask
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226 ; GCN: buffer_store_dword
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121
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227 define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_eq_0(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind {
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228 %tid = call i32 @llvm.r600.read.tidig.x()
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229 %in.gep = getelementptr i32, i32 addrspace(1)* %valptr, i32 %tid
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230 %val = load i32, i32 addrspace(1)* %in.gep
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100
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231 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 true) nounwind readnone
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232 %cmp = icmp eq i32 %val, 0
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233 %sel = select i1 %cmp, i32 0, i32 %ctlz
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234 store i32 %sel, i32 addrspace(1)* %out
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235 ret void
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236 }
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237
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238 ; Selected on wrong constant
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239 ; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i32_sel_ne_0:
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121
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240 ; GCN: {{buffer|flat}}_load_dword
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120
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241 ; GCN: v_ffbh_u32_e32
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242 ; GCN: v_cmp
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243 ; GCN: v_cndmask
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244 ; GCN: buffer_store_dword
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121
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245 define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_ne_0(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind {
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246 %tid = call i32 @llvm.r600.read.tidig.x()
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247 %in.gep = getelementptr i32, i32 addrspace(1)* %valptr, i32 %tid
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248 %val = load i32, i32 addrspace(1)* %in.gep
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100
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249 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 true) nounwind readnone
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250 %cmp = icmp ne i32 %val, 0
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251 %sel = select i1 %cmp, i32 %ctlz, i32 0
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252 store i32 %sel, i32 addrspace(1)* %out
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253 ret void
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254 }
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255
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256 ; Compare on wrong constant
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257 ; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i32_sel_eq_cmp_non0:
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121
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258 ; GCN: {{buffer|flat}}_load_dword
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120
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259 ; GCN: v_ffbh_u32_e32
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260 ; GCN: v_cmp
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261 ; GCN: v_cndmask
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262 ; GCN: buffer_store_dword
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121
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263 define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_eq_cmp_non0(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind {
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264 %tid = call i32 @llvm.r600.read.tidig.x()
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265 %in.gep = getelementptr i32, i32 addrspace(1)* %valptr, i32 %tid
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266 %val = load i32, i32 addrspace(1)* %in.gep
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100
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267 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 true) nounwind readnone
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268 %cmp = icmp eq i32 %val, 1
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269 %sel = select i1 %cmp, i32 0, i32 %ctlz
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270 store i32 %sel, i32 addrspace(1)* %out
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271 ret void
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272 }
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273
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274 ; Selected on wrong constant
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275 ; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i32_sel_ne_cmp_non0:
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121
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276 ; GCN: {{buffer|flat}}_load_dword
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120
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277 ; GCN: v_ffbh_u32_e32
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278 ; GCN: v_cmp
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279 ; GCN: v_cndmask
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280 ; GCN: buffer_store_dword
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121
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281 define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_ne_cmp_non0(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind {
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282 %tid = call i32 @llvm.r600.read.tidig.x()
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283 %in.gep = getelementptr i32, i32 addrspace(1)* %valptr, i32 %tid
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284 %val = load i32, i32 addrspace(1)* %in.gep
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100
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285 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 true) nounwind readnone
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286 %cmp = icmp ne i32 %val, 1
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287 %sel = select i1 %cmp, i32 %ctlz, i32 0
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288 store i32 %sel, i32 addrspace(1)* %out
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289 ret void
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290 }
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