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120
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1 # RUN: llc -march=amdgcn -run-pass detect-dead-lanes -o - %s | FileCheck %s
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2 ...
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3 ---
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4 # Combined use/def transfer check, the basics.
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5 # CHECK-LABEL: name: test0
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6 # CHECK: S_NOP 0, implicit-def %0
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7 # CHECK: S_NOP 0, implicit-def %1
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8 # CHECK: S_NOP 0, implicit-def dead %2
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121
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9 # CHECK: %3:sreg_128 = REG_SEQUENCE %0, {{[0-9]+}}, %1, {{[0-9]+}}, undef %2, {{[0-9]+}}
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120
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10 # CHECK: S_NOP 0, implicit %3.sub0
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11 # CHECK: S_NOP 0, implicit %3.sub1
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12 # CHECK: S_NOP 0, implicit undef %3.sub2
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121
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13 # CHECK: %4:sreg_64 = COPY %3.sub0_sub1
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14 # CHECK: %5:sreg_64 = COPY undef %3.sub2_sub3
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120
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15 # CHECK: S_NOP 0, implicit %4.sub0
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16 # CHECK: S_NOP 0, implicit %4.sub1
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17 # CHECK: S_NOP 0, implicit undef %5.sub0
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18 name: test0
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19 registers:
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20 - { id: 0, class: sreg_32_xm0 }
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21 - { id: 1, class: sreg_32_xm0 }
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22 - { id: 2, class: sreg_32_xm0 }
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23 - { id: 3, class: sreg_128 }
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24 - { id: 4, class: sreg_64 }
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25 - { id: 5, class: sreg_64 }
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26 body: |
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27 bb.0:
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28 S_NOP 0, implicit-def %0
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29 S_NOP 0, implicit-def %1
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30 S_NOP 0, implicit-def %2
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31 %3 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub3
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32 S_NOP 0, implicit %3.sub0
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33 S_NOP 0, implicit %3.sub1
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34 S_NOP 0, implicit %3.sub2
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35 %4 = COPY %3.sub0_sub1
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36 %5 = COPY %3.sub2_sub3
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37 S_NOP 0, implicit %4.sub0
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38 S_NOP 0, implicit %4.sub1
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39 S_NOP 0, implicit %5.sub0
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40 ...
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41 ---
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42 # Check defined lanes transfer; Includes checking for some special cases like
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43 # undef operands or IMPLICIT_DEF definitions.
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44 # CHECK-LABEL: name: test1
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121
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45 # CHECK: %0:sreg_128 = REG_SEQUENCE %sgpr0, {{[0-9]+}}, %sgpr0, {{[0-9]+}}
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46 # CHECK: %1:sreg_128 = INSERT_SUBREG %0, %sgpr1, {{[0-9]+}}
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47 # CHECK: %2:sreg_64 = INSERT_SUBREG %0.sub2_sub3, %sgpr42, {{[0-9]+}}
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120
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48 # CHECK: S_NOP 0, implicit %1.sub0
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49 # CHECK: S_NOP 0, implicit undef %1.sub1
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50 # CHECK: S_NOP 0, implicit %1.sub2
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51 # CHECK: S_NOP 0, implicit %1.sub3
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52 # CHECK: S_NOP 0, implicit %2.sub0
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53 # CHECK: S_NOP 0, implicit undef %2.sub1
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54
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121
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55 # CHECK: %3:sreg_32_xm0 = IMPLICIT_DEF
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56 # CHECK: %4:sreg_128 = INSERT_SUBREG %0, undef %3, {{[0-9]+}}
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120
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57 # CHECK: S_NOP 0, implicit undef %4.sub0
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58 # CHECK: S_NOP 0, implicit undef %4.sub1
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59 # CHECK: S_NOP 0, implicit %4.sub2
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60 # CHECK: S_NOP 0, implicit undef %4.sub3
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61
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121
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62 # CHECK: %5:sreg_64 = EXTRACT_SUBREG %0, {{[0-9]+}}
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63 # CHECK: %6:sreg_32_xm0 = EXTRACT_SUBREG %5, {{[0-9]+}}
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64 # CHECK: %7:sreg_32_xm0 = EXTRACT_SUBREG %5, {{[0-9]+}}
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120
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65 # CHECK: S_NOP 0, implicit %5
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66 # CHECK: S_NOP 0, implicit %6
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67 # CHECK: S_NOP 0, implicit undef %7
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68
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121
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69 # CHECK: %8:sreg_64 = IMPLICIT_DEF
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70 # CHECK: %9:sreg_32_xm0 = EXTRACT_SUBREG undef %8, {{[0-9]+}}
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120
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71 # CHECK: S_NOP 0, implicit undef %9
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72
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121
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73 # CHECK: %10:sreg_128 = EXTRACT_SUBREG undef %0, {{[0-9]+}}
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120
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74 # CHECK: S_NOP 0, implicit undef %10
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75 name: test1
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76 registers:
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77 - { id: 0, class: sreg_128 }
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78 - { id: 1, class: sreg_128 }
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79 - { id: 2, class: sreg_64 }
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80 - { id: 3, class: sreg_32_xm0 }
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81 - { id: 4, class: sreg_128 }
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82 - { id: 5, class: sreg_64 }
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83 - { id: 6, class: sreg_32_xm0 }
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84 - { id: 7, class: sreg_32_xm0 }
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85 - { id: 8, class: sreg_64 }
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86 - { id: 9, class: sreg_32_xm0 }
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87 - { id: 10, class: sreg_128 }
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88 body: |
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89 bb.0:
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90 %0 = REG_SEQUENCE %sgpr0, %subreg.sub0, %sgpr0, %subreg.sub2
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91 %1 = INSERT_SUBREG %0, %sgpr1, %subreg.sub3
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92 %2 = INSERT_SUBREG %0.sub2_sub3, %sgpr42, %subreg.sub0
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93 S_NOP 0, implicit %1.sub0
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94 S_NOP 0, implicit %1.sub1
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95 S_NOP 0, implicit %1.sub2
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96 S_NOP 0, implicit %1.sub3
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97 S_NOP 0, implicit %2.sub0
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98 S_NOP 0, implicit %2.sub1
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99
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100 %3 = IMPLICIT_DEF
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101 %4 = INSERT_SUBREG %0, %3, %subreg.sub0
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102 S_NOP 0, implicit %4.sub0
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103 S_NOP 0, implicit %4.sub1
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104 S_NOP 0, implicit %4.sub2
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105 S_NOP 0, implicit %4.sub3
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106
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107 %5 = EXTRACT_SUBREG %0, %subreg.sub0_sub1
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108 %6 = EXTRACT_SUBREG %5, %subreg.sub0
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109 %7 = EXTRACT_SUBREG %5, %subreg.sub1
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110 S_NOP 0, implicit %5
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111 S_NOP 0, implicit %6
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112 S_NOP 0, implicit %7
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113
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114 %8 = IMPLICIT_DEF
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115 %9 = EXTRACT_SUBREG %8, %subreg.sub1
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116 S_NOP 0, implicit %9
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117
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118 %10 = EXTRACT_SUBREG undef %0, %subreg.sub2_sub3
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119 S_NOP 0, implicit %10
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120 ...
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121 ---
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122 # Check used lanes transfer; Includes checking for some special cases like
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123 # undef operands.
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124 # CHECK-LABEL: name: test2
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125 # CHECK: S_NOP 0, implicit-def dead %0
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126 # CHECK: S_NOP 0, implicit-def %1
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127 # CHECK: S_NOP 0, implicit-def %2
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121
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128 # CHECK: %3:sreg_128 = REG_SEQUENCE undef %0, {{[0-9]+}}, %1, {{[0-9]+}}, %2, {{[0-9]+}}
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120
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129 # CHECK: S_NOP 0, implicit %3.sub1
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130 # CHECK: S_NOP 0, implicit %3.sub3
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131
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132 # CHECK: S_NOP 0, implicit-def %4
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133 # CHECK: S_NOP 0, implicit-def dead %5
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121
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134 # CHECK: %6:sreg_64 = REG_SEQUENCE %4, {{[0-9]+}}, undef %5, {{[0-9]+}}
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120
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135 # CHECK: S_NOP 0, implicit %6
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136
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137 # CHECK: S_NOP 0, implicit-def dead %7
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138 # CHECK: S_NOP 0, implicit-def %8
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121
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139 # CHECK: %9:sreg_128 = INSERT_SUBREG undef %7, %8, {{[0-9]+}}
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120
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140 # CHECK: S_NOP 0, implicit %9.sub2
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141
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142 # CHECK: S_NOP 0, implicit-def %10
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143 # CHECK: S_NOP 0, implicit-def dead %11
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121
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144 # CHECK: %12:sreg_128 = INSERT_SUBREG %10, undef %11, {{[0-9]+}}
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120
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145 # CHECK: S_NOP 0, implicit %12.sub3
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146
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147 # CHECK: S_NOP 0, implicit-def %13
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148 # CHECK: S_NOP 0, implicit-def dead %14
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121
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149 # CHECK: %15:sreg_128 = REG_SEQUENCE %13, {{[0-9]+}}, undef %14, {{[0-9]+}}
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150 # CHECK: %16:sreg_64 = EXTRACT_SUBREG %15, {{[0-9]+}}
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120
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151 # CHECK: S_NOP 0, implicit %16.sub1
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152
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153 name: test2
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154 registers:
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155 - { id: 0, class: sreg_32_xm0 }
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156 - { id: 1, class: sreg_32_xm0 }
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157 - { id: 2, class: sreg_64 }
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158 - { id: 3, class: sreg_128 }
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159 - { id: 4, class: sreg_32_xm0 }
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160 - { id: 5, class: sreg_32_xm0 }
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161 - { id: 6, class: sreg_64 }
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162 - { id: 7, class: sreg_128 }
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163 - { id: 8, class: sreg_64 }
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164 - { id: 9, class: sreg_128 }
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165 - { id: 10, class: sreg_128 }
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166 - { id: 11, class: sreg_64 }
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167 - { id: 12, class: sreg_128 }
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168 - { id: 13, class: sreg_64 }
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169 - { id: 14, class: sreg_64 }
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170 - { id: 15, class: sreg_128 }
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171 - { id: 16, class: sreg_64 }
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172 body: |
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173 bb.0:
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174 S_NOP 0, implicit-def %0
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175 S_NOP 0, implicit-def %1
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176 S_NOP 0, implicit-def %2
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177 %3 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2_sub3
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178 S_NOP 0, implicit %3.sub1
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179 S_NOP 0, implicit %3.sub3
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180
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181 S_NOP 0, implicit-def %4
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182 S_NOP 0, implicit-def %5
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183 %6 = REG_SEQUENCE %4, %subreg.sub0, undef %5, %subreg.sub1
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184 S_NOP 0, implicit %6
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185
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186 S_NOP 0, implicit-def %7
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187 S_NOP 0, implicit-def %8
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188 %9 = INSERT_SUBREG %7, %8, %subreg.sub2_sub3
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189 S_NOP 0, implicit %9.sub2
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190
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191 S_NOP 0, implicit-def %10
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192 S_NOP 0, implicit-def %11
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193 %12 = INSERT_SUBREG %10, %11, %subreg.sub0_sub1
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194 S_NOP 0, implicit %12.sub3
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195
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196 S_NOP 0, implicit-def %13
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197 S_NOP 0, implicit-def %14
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198 %15 = REG_SEQUENCE %13, %subreg.sub0_sub1, %14, %subreg.sub2_sub3
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199 %16 = EXTRACT_SUBREG %15, %subreg.sub0_sub1
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200 S_NOP 0, implicit %16.sub1
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201 ...
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202 ---
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203 # Check that copies to physregs use all lanes, copies from physregs define all
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204 # lanes. So we should not get a dead/undef flag here.
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205 # CHECK-LABEL: name: test3
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206 # CHECK: S_NOP 0, implicit-def %0
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207 # CHECK: %vcc = COPY %0
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121
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208 # CHECK: %1:sreg_64 = COPY %vcc
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120
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209 # CHECK: S_NOP 0, implicit %1
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210 name: test3
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211 tracksRegLiveness: true
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212 registers:
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213 - { id: 0, class: sreg_64 }
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214 - { id: 1, class: sreg_64 }
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215 body: |
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216 bb.0:
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217 S_NOP 0, implicit-def %0
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218 %vcc = COPY %0
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219
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220 %1 = COPY %vcc
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221 S_NOP 0, implicit %1
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222 ...
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223 ---
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224 # Check that implicit-def/kill do not count as def/uses.
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225 # CHECK-LABEL: name: test4
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226 # CHECK: S_NOP 0, implicit-def dead %0
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227 # CHECK: KILL undef %0
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121
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228 # CHECK: %1:sreg_64 = IMPLICIT_DEF
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120
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229 # CHECK: S_NOP 0, implicit undef %1
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230 name: test4
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231 tracksRegLiveness: true
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232 registers:
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233 - { id: 0, class: sreg_64 }
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234 - { id: 1, class: sreg_64 }
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235 body: |
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236 bb.0:
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237 S_NOP 0, implicit-def %0
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238 KILL %0
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239
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240 %1 = IMPLICIT_DEF
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241 S_NOP 0, implicit %1
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242 ...
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243 ---
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244 # Check that unused inputs are marked as undef, even if the vreg itself is
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245 # used.
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246 # CHECK-LABEL: name: test5
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247 # CHECK: S_NOP 0, implicit-def %0
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121
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248 # CHECK: %1:sreg_64 = REG_SEQUENCE undef %0, {{[0-9]+}}, %0, {{[0-9]+}}
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120
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249 # CHECK: S_NOP 0, implicit %1.sub1
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250 name: test5
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251 tracksRegLiveness: true
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252 registers:
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253 - { id: 0, class: sreg_32_xm0 }
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254 - { id: 1, class: sreg_64 }
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255 body: |
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256 bb.0:
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257 S_NOP 0, implicit-def %0
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258 %1 = REG_SEQUENCE %0, %subreg.sub0, %0, %subreg.sub1
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259 S_NOP 0, implicit %1.sub1
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260 ...
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261 ---
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262 # Check "optimistic" dataflow fixpoint in phi-loops.
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263 # CHECK-LABEL: name: loop0
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264 # CHECK: bb.0:
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265 # CHECK: S_NOP 0, implicit-def %0
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266 # CHECK: S_NOP 0, implicit-def dead %1
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267 # CHECK: S_NOP 0, implicit-def dead %2
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121
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268 # CHECK: %3:sreg_128 = REG_SEQUENCE %0, {{[0-9]+}}, undef %1, {{[0-9]+}}, undef %2, {{[0-9]+}}
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120
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269
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270 # CHECK: bb.1:
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121
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271 # CHECK: %4:sreg_128 = PHI %3, %bb.0, %5, %bb.1
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120
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272
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273 # CHECK: bb.2:
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274 # CHECK: S_NOP 0, implicit %4.sub0
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275 # CHECK: S_NOP 0, implicit undef %4.sub3
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276 name: loop0
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277 tracksRegLiveness: true
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278 registers:
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279 - { id: 0, class: sreg_32_xm0 }
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280 - { id: 1, class: sreg_32_xm0 }
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281 - { id: 2, class: sreg_32_xm0 }
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282 - { id: 3, class: sreg_128 }
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283 - { id: 4, class: sreg_128 }
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284 - { id: 5, class: sreg_128 }
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285 body: |
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286 bb.0:
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287 S_NOP 0, implicit-def %0
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288 S_NOP 0, implicit-def %1
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289 S_NOP 0, implicit-def %2
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290 %3 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2
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291 S_BRANCH %bb.1
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292
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293 bb.1:
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294 %4 = PHI %3, %bb.0, %5, %bb.1
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295
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296 ; let's swiffle some lanes around for fun...
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297 %5 = REG_SEQUENCE %4.sub0, %subreg.sub0, %4.sub2, %subreg.sub1, %4.sub1, %subreg.sub2, %4.sub3, %subreg.sub3
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298
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299 S_CBRANCH_VCCNZ %bb.1, implicit undef %vcc
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300 S_BRANCH %bb.2
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301
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302 bb.2:
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303 S_NOP 0, implicit %4.sub0
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304 S_NOP 0, implicit %4.sub3
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305 ...
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306 ---
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307 # Check a loop that needs to be traversed multiple times to reach the fixpoint
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308 # for the used lanes. The example reads sub3 lane at the end, however with each
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309 # loop iteration we should get 1 more lane marked as we cycles the sublanes
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310 # along. Sublanes sub0, sub1 and sub3 are rotate in the loop so only sub2
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311 # should be dead.
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312 # CHECK-LABEL: name: loop1
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313 # CHECK: bb.0:
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314 # CHECK: S_NOP 0, implicit-def %0
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315 # CHECK: S_NOP 0, implicit-def %1
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316 # CHECK: S_NOP 0, implicit-def dead %2
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317 # CHECK: S_NOP 0, implicit-def %3
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121
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318 # CHECK: %4:sreg_128 = REG_SEQUENCE %0, {{[0-9]+}}, %1, {{[0-9]+}}, undef %2, {{[0-9]+}}, %3, {{[0-9]+}}
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120
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319
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320 # CHECK: bb.1:
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121
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321 # CHECK: %5:sreg_128 = PHI %4, %bb.0, %6, %bb.1
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120
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322
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121
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323 # CHECK: %6:sreg_128 = REG_SEQUENCE %5.sub1, {{[0-9]+}}, %5.sub3, {{[0-9]+}}, undef %5.sub2, {{[0-9]+}}, %5.sub0, {{[0-9]+}}
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120
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324
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325 # CHECK: bb.2:
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326 # CHECK: S_NOP 0, implicit %6.sub3
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327 name: loop1
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328 tracksRegLiveness: true
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329 registers:
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330 - { id: 0, class: sreg_32_xm0 }
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331 - { id: 1, class: sreg_32_xm0 }
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332 - { id: 2, class: sreg_32_xm0 }
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333 - { id: 3, class: sreg_32_xm0 }
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334 - { id: 4, class: sreg_128 }
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335 - { id: 5, class: sreg_128 }
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336 - { id: 6, class: sreg_128 }
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337 body: |
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338 bb.0:
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339 S_NOP 0, implicit-def %0
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340 S_NOP 0, implicit-def %1
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341 S_NOP 0, implicit-def dead %2
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342 S_NOP 0, implicit-def %3
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343 %4 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3
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344 S_BRANCH %bb.1
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345
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346 bb.1:
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347 %5 = PHI %4, %bb.0, %6, %bb.1
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348
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349 ; rotate lanes, but skip sub2 lane...
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350 %6 = REG_SEQUENCE %5.sub1, %subreg.sub0, %5.sub3, %subreg.sub1, %5.sub2, %subreg.sub2, %5.sub0, %subreg.sub3
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351
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352 S_CBRANCH_VCCNZ %bb.1, implicit undef %vcc
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353 S_BRANCH %bb.2
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354
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355 bb.2:
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356 S_NOP 0, implicit %6.sub3
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357 ...
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358 ---
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359 # Similar to loop1 test, but check for fixpoint of defined lanes.
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360 # Lanes are rotate between sub0, sub2, sub3 so only sub1 should be dead/undef.
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361 # CHECK-LABEL: name: loop2
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362 # CHECK: bb.0:
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363 # CHECK: S_NOP 0, implicit-def %0
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121
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364 # CHECK: %1:sreg_128 = REG_SEQUENCE %0, {{[0-9]+}}
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120
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365
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366 # CHECK: bb.1:
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121
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367 # CHECK: %2:sreg_128 = PHI %1, %bb.0, %3, %bb.1
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120
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368
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121
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369 # CHECK: %3:sreg_128 = REG_SEQUENCE %2.sub3, {{[0-9]+}}, undef %2.sub1, {{[0-9]+}}, %2.sub0, {{[0-9]+}}, %2.sub2, {{[0-9]+}}
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120
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370
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371 # CHECK: bb.2:
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372 # CHECK: S_NOP 0, implicit %2.sub0
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373 # CHECK: S_NOP 0, implicit undef %2.sub1
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374 # CHECK: S_NOP 0, implicit %2.sub2
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375 # CHECK: S_NOP 0, implicit %2.sub3
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376 name: loop2
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377 tracksRegLiveness: true
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378 registers:
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379 - { id: 0, class: sreg_32_xm0 }
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380 - { id: 1, class: sreg_128 }
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381 - { id: 2, class: sreg_128 }
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382 - { id: 3, class: sreg_128 }
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383 body: |
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384 bb.0:
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385 S_NOP 0, implicit-def %0
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386 %1 = REG_SEQUENCE %0, %subreg.sub0
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387 S_BRANCH %bb.1
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388
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389 bb.1:
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390 %2 = PHI %1, %bb.0, %3, %bb.1
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391
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392 ; rotate subreg lanes, skipping sub1
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393 %3 = REG_SEQUENCE %2.sub3, %subreg.sub0, %2.sub1, %subreg.sub1, %2.sub0, %subreg.sub2, %2.sub2, %subreg.sub3
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394
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395 S_CBRANCH_VCCNZ %bb.1, implicit undef %vcc
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396 S_BRANCH %bb.2
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397
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398 bb.2:
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399 S_NOP 0, implicit %2.sub0
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400 S_NOP 0, implicit undef %2.sub1
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401 S_NOP 0, implicit %2.sub2
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402 S_NOP 0, implicit %2.sub3
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403 ...
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