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121
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1 # RUN: llc -march=amdgcn -verify-machineinstrs -run-pass si-optimize-exec-masking-pre-ra %s -o - | FileCheck -check-prefix=GCN %s
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2
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3 # GCN-LABEL: name: kill_all
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4 # GCN: bb.0:
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5 # GCN-NEXT: S_ENDPGM
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6 name: kill_all
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7 tracksRegLiveness: true
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8 registers:
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9 - { id: 0, class: vreg_64 }
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10 - { id: 1, class: vgpr_32 }
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11 - { id: 2, class: vgpr_32 }
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12 - { id: 3, class: sgpr_32 }
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13 - { id: 4, class: sgpr_32 }
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14 body: |
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15 bb.0:
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16 %vcc = IMPLICIT_DEF
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17 %0 = IMPLICIT_DEF
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18 %3 = IMPLICIT_DEF
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19 %sgpr0_sgpr1 = S_OR_B64 %exec, killed %vcc, implicit-def %scc
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20 %1 = FLAT_LOAD_DWORD %0, 0, 0, 0, implicit %exec, implicit %flat_scr :: (load 4)
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21 %2 = V_ADD_F32_e64 0, killed %1, 0, 1, 0, 0, implicit %exec
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22 %4 = S_ADD_U32 %3, 1, implicit-def %scc
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23 S_ENDPGM
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24 ...
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25 ---
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26 # GCN-LABEL: name: load_without_memoperand
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27 # GCN: %sgpr0_sgpr1 = S_OR_B64 %exec, killed %vcc, implicit-def %scc
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28 # GCN-NEXT: dead %1:vgpr_32 = FLAT_LOAD_DWORD %0, 0, 0, 0, implicit %exec, implicit %flat_scr
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29 # GCN-NEXT: S_ENDPGM
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30 name: load_without_memoperand
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31 tracksRegLiveness: true
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32 registers:
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33 - { id: 0, class: vreg_64 }
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34 - { id: 1, class: vgpr_32 }
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35 - { id: 2, class: vgpr_32 }
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36 - { id: 3, class: sgpr_32 }
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37 - { id: 4, class: sgpr_32 }
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38 body: |
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39 bb.0:
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40 %vcc = IMPLICIT_DEF
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41 %0 = IMPLICIT_DEF
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42 %3 = IMPLICIT_DEF
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43 %sgpr0_sgpr1 = S_OR_B64 %exec, killed %vcc, implicit-def %scc
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44 %1 = FLAT_LOAD_DWORD %0, 0, 0, 0, implicit %exec, implicit %flat_scr
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45 %2 = V_ADD_F32_e64 0, killed %1, 0, 1, 0, 0, implicit %exec
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46 %4 = S_ADD_U32 %3, 1, implicit-def %scc
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47 S_ENDPGM
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48 ...
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49 ---
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50 # GCN-LABEL: name: load_volatile
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51 # GCN: %sgpr0_sgpr1 = S_OR_B64 %exec, killed %vcc, implicit-def %scc
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52 # GCN-NEXT: dead %1:vgpr_32 = FLAT_LOAD_DWORD %0, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile load 4)
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53 # GCN-NEXT: S_ENDPGM
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54 name: load_volatile
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55 tracksRegLiveness: true
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56 registers:
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57 - { id: 0, class: vreg_64 }
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58 - { id: 1, class: vgpr_32 }
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59 - { id: 2, class: vgpr_32 }
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60 - { id: 3, class: sgpr_32 }
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61 - { id: 4, class: sgpr_32 }
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62 body: |
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63 bb.0:
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64 %vcc = IMPLICIT_DEF
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65 %0 = IMPLICIT_DEF
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66 %3 = IMPLICIT_DEF
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67 %sgpr0_sgpr1 = S_OR_B64 %exec, killed %vcc, implicit-def %scc
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68 %1 = FLAT_LOAD_DWORD %0, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile load 4)
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69 %2 = V_ADD_F32_e64 0, killed %1, 0, 1, 0, 0, implicit %exec
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70 %4 = S_ADD_U32 %3, 1, implicit-def %scc
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71 S_ENDPGM
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72 ...
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73 ---
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74 # GCN-LABEL: name: store
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75 # GCN: %sgpr0_sgpr1 = S_OR_B64 %exec, killed %vcc, implicit-def %scc
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76 # GCN-NEXT: FLAT_STORE_DWORD %0, %1, 0, 0, 0, implicit %exec, implicit %flat_scr :: (store 4)
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77 # GCN-NEXT: S_ENDPGM
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78 name: store
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79 tracksRegLiveness: true
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80 registers:
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81 - { id: 0, class: vreg_64 }
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82 - { id: 1, class: vgpr_32 }
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83 body: |
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84 bb.0:
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85 %vcc = IMPLICIT_DEF
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86 %0 = IMPLICIT_DEF
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87 %1 = IMPLICIT_DEF
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88 %sgpr0_sgpr1 = S_OR_B64 %exec, killed %vcc, implicit-def %scc
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89 FLAT_STORE_DWORD %0, %1, 0, 0, 0, implicit %exec, implicit %flat_scr :: (store 4)
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90 S_ENDPGM
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91 ...
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92 ---
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93 # GCN-LABEL: name: barrier
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94 # GCN: %sgpr0_sgpr1 = S_OR_B64 %exec, killed %vcc, implicit-def %scc
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95 # GCN-NEXT: S_BARRIER
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96 # GCN-NEXT: S_ENDPGM
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97 name: barrier
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98 tracksRegLiveness: true
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99 body: |
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100 bb.0:
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101 %vcc = IMPLICIT_DEF
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102 %sgpr0_sgpr1 = S_OR_B64 %exec, killed %vcc, implicit-def %scc
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103 S_BARRIER
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104 S_ENDPGM
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105 ...
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106 ---
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107 # GCN-LABEL: name: call
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108 # GCN: %sgpr0_sgpr1 = S_OR_B64 %exec, killed %vcc, implicit-def %scc
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109 # GCN-NEXT: %sgpr4_sgpr5 = S_SWAPPC_B64 %sgpr2_sgpr3
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110 # GCN-NEXT: S_ENDPGM
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111 name: call
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112 tracksRegLiveness: true
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113 body: |
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114 bb.0:
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115 %vcc = IMPLICIT_DEF
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116 %sgpr0_sgpr1 = S_OR_B64 %exec, killed %vcc, implicit-def %scc
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117 %sgpr4_sgpr5 = S_SWAPPC_B64 %sgpr2_sgpr3
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118 S_ENDPGM
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119 ...
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120 ---
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121 # GCN-LABEL: name: exp
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122 # GCN: %sgpr0_sgpr1 = S_OR_B64 %exec, killed %vcc, implicit-def %scc
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123 # GCN-NEXT: EXP 32, undef %0:vgpr_32, undef %1:vgpr_32, %2, undef %3:vgpr_32, 0, 0, 15, implicit %exec
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124 # GCN-NEXT: S_ENDPGM
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125 name: exp
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126 tracksRegLiveness: true
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127 registers:
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128 - { id: 0, class: vgpr_32 }
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129 - { id: 1, class: vgpr_32 }
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130 - { id: 2, class: vgpr_32 }
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131 - { id: 3, class: vgpr_32 }
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132 body: |
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133 bb.0:
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134 %vcc = IMPLICIT_DEF
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135 %2 = IMPLICIT_DEF
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136 %sgpr0_sgpr1 = S_OR_B64 %exec, killed %vcc, implicit-def %scc
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137 EXP 32, undef %0, undef %1, killed %2, undef %3, 0, 0, 15, implicit %exec
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138 S_ENDPGM
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139 ...
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140 ---
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141 # GCN-LABEL: name: return_to_epilog
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142 # GCN: %sgpr0_sgpr1 = S_OR_B64 %exec, killed %vcc, implicit-def %scc
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143 # GCN-NEXT: SI_RETURN_TO_EPILOG killed %vgpr0
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144 name: return_to_epilog
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145 tracksRegLiveness: true
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146 body: |
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147 bb.0:
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148 %vcc = IMPLICIT_DEF
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149 %vgpr0 = IMPLICIT_DEF
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150 %sgpr0_sgpr1 = S_OR_B64 %exec, killed %vcc, implicit-def %scc
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151 SI_RETURN_TO_EPILOG killed %vgpr0
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152 ...
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153 ---
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154 # GCN-LABEL: name: split_block
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155 # GCN: bb.0:
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156 # GCN-NEXT: successors: %bb.1
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157 # GCN-NOT: S_OR_B64
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158 # GCN: bb.1:
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159 # GCN-NEXT: S_ENDPGM
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160 name: split_block
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161 tracksRegLiveness: true
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162 registers:
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163 - { id: 0, class: vgpr_32 }
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164 - { id: 1, class: vgpr_32 }
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165 - { id: 2, class: sgpr_32 }
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166 - { id: 3, class: sgpr_32 }
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167 body: |
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168 bb.0:
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169 %vcc = IMPLICIT_DEF
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170 %sgpr0_sgpr1 = S_OR_B64 %exec, killed %vcc, implicit-def %scc
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171
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172 bb.1:
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173 %0 = IMPLICIT_DEF
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174 %2 = IMPLICIT_DEF
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175 %1 = V_ADD_F32_e64 0, killed %0, 0, 1, 0, 0, implicit %exec
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176 %3 = S_ADD_U32 %2, 1, implicit-def %scc
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177 S_ENDPGM
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178 ...
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179 ---
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180 # GCN-LABEL: name: split_block_empty_block
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181 # GCN: bb.0:
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182 # GCN-NEXT: successors: %bb.1
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183 # GCN-NOT: S_OR_B64
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184 # GCN: bb.1:
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185 # GCN: bb.2:
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186 # GCN-NEXT: S_ENDPGM
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187 name: split_block_empty_block
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188 tracksRegLiveness: true
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189 body: |
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190 bb.0:
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191 %vcc = IMPLICIT_DEF
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192 %sgpr0_sgpr1 = S_OR_B64 %exec, killed %vcc, implicit-def %scc
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193
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194 bb.1:
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195
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196 bb.2:
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197 S_ENDPGM
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198 ...
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199 ---
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200 # GCN-LABEL: name: split_block_uncond_branch
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201 # GCN: bb.0:
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202 # GCN-NEXT: successors: %bb.1
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203 # GCN: S_BRANCH %bb.1
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204 # GCN-NOT: S_OR_B64
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205 # GCN: bb.1:
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206 # GCN-NEXT: S_ENDPGM
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207 name: split_block_uncond_branch
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208 tracksRegLiveness: true
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209 body: |
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210 bb.0:
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211 %vcc = IMPLICIT_DEF
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212 %sgpr0_sgpr1 = S_OR_B64 %exec, killed %vcc, implicit-def %scc
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213 S_BRANCH %bb.1
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214
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215 bb.1:
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216 S_ENDPGM
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217 ...
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218 ---
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219 # GCN-LABEL: name: split_block_cond_branch
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220 # GCN: bb.0:
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221 # GCN-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
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222 # GCN: %sgpr0_sgpr1 = S_OR_B64 %exec, %vcc, implicit-def %scc
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223 # GCN: S_CBRANCH_VCCNZ %bb.2, implicit undef %vcc
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224 # GCN: bb.1:
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225 # GCN: bb.2:
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226 # GCN-NEXT: S_ENDPGM
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227 name: split_block_cond_branch
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228 tracksRegLiveness: true
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229 body: |
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230 bb.0:
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231 %vcc = IMPLICIT_DEF
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232 %sgpr0_sgpr1 = S_OR_B64 %exec, %vcc, implicit-def %scc
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233 S_CBRANCH_VCCNZ %bb.2, implicit undef %vcc
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234
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235 bb.1:
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236
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237 bb.2:
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238 S_ENDPGM
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239 ...
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240 ---
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241 # GCN-LABEL: name: two_preds_both_dead
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242 # GCN: bb.0:
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243 # GCN-NEXT: successors: %bb.2
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244 # GCN-NOT: S_OR
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245 # GCN: S_BRANCH %bb.2
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246 # GCN: bb.1:
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247 # GCN-NEXT: successors: %bb.2
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248 # GCN-NOT: S_AND
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249 # GCN: S_BRANCH %bb.2
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250 # GCN: bb.2:
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251 # GCN-NEXT: S_ENDPGM
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252 name: two_preds_both_dead
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253 tracksRegLiveness: true
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254 body: |
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255 bb.0:
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256 %vcc = IMPLICIT_DEF
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257 %sgpr0_sgpr1 = S_OR_B64 %exec, killed %vcc, implicit-def %scc
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258 S_BRANCH %bb.2
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259
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260 bb.1:
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261 %vcc = IMPLICIT_DEF
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262 %sgpr0_sgpr1 = S_AND_B64 %exec, killed %vcc, implicit-def %scc
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263 S_BRANCH %bb.2
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264
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265 bb.2:
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266 S_ENDPGM
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267 ...
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268 ---
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269 # GCN-LABEL: name: two_preds_one_dead
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270 # GCN: bb.0:
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271 # GCN-NEXT: successors: %bb.2
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272 # GCN: %sgpr0_sgpr1 = S_OR_B64 %exec, killed %vcc, implicit-def %scc
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273 # GCN-NEXT: S_BARRIER
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274 # GCN-NEXT: S_BRANCH %bb.2
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275 # GCN: bb.1:
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276 # GCN-NEXT: successors: %bb.2
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277 # GCN-NOT: S_AND
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278 # GCN: S_BRANCH %bb.2
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279 # GCN: bb.2:
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280 # GCN-NEXT: S_ENDPGM
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281 name: two_preds_one_dead
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282 tracksRegLiveness: true
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283 body: |
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284 bb.0:
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285 %vcc = IMPLICIT_DEF
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286 %sgpr0_sgpr1 = S_OR_B64 %exec, killed %vcc, implicit-def %scc
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287 S_BARRIER
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288 S_BRANCH %bb.2
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289
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290 bb.1:
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291 %vcc = IMPLICIT_DEF
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292 %sgpr0_sgpr1 = S_AND_B64 %exec, killed %vcc, implicit-def %scc
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293 S_BRANCH %bb.2
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294
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295 bb.2:
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296 S_ENDPGM
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297 ...
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