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120
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1 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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2
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3 ; GCN-LABEL: {{^}}store_build_vector_multiple_uses_v4i32:
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4 ; GCN: buffer_load_dword
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5 ; GCN: buffer_load_dword
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6 ; GCN: buffer_load_dword
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7 ; GCN: buffer_load_dword
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8
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9 ; GCN: buffer_store_dwordx4
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10 ; GCN: buffer_store_dwordx4
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11
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12 ; GCN: buffer_store_dword
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13 ; GCN: buffer_store_dword
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14 ; GCN: buffer_store_dword
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15 ; GCN: buffer_store_dword
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121
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16 define amdgpu_kernel void @store_build_vector_multiple_uses_v4i32(<4 x i32> addrspace(1)* noalias %out0,
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120
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17 <4 x i32> addrspace(1)* noalias %out1,
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18 i32 addrspace(1)* noalias %out2,
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19 i32 addrspace(1)* %in) {
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20 %elt0 = load volatile i32, i32 addrspace(1)* %in
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21 %elt1 = load volatile i32, i32 addrspace(1)* %in
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22 %elt2 = load volatile i32, i32 addrspace(1)* %in
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23 %elt3 = load volatile i32, i32 addrspace(1)* %in
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24
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25 %vec0 = insertelement <4 x i32> undef, i32 %elt0, i32 0
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26 %vec1 = insertelement <4 x i32> %vec0, i32 %elt1, i32 1
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27 %vec2 = insertelement <4 x i32> %vec1, i32 %elt2, i32 2
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28 %vec3 = insertelement <4 x i32> %vec2, i32 %elt3, i32 3
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29
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30 store <4 x i32> %vec3, <4 x i32> addrspace(1)* %out0
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31 store <4 x i32> %vec3, <4 x i32> addrspace(1)* %out1
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32
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33 %extract0 = extractelement <4 x i32> %vec3, i32 0
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34 %extract1 = extractelement <4 x i32> %vec3, i32 1
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35 %extract2 = extractelement <4 x i32> %vec3, i32 2
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36 %extract3 = extractelement <4 x i32> %vec3, i32 3
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37
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38 store volatile i32 %extract0, i32 addrspace(1)* %out2
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39 store volatile i32 %extract1, i32 addrspace(1)* %out2
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40 store volatile i32 %extract2, i32 addrspace(1)* %out2
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41 store volatile i32 %extract3, i32 addrspace(1)* %out2
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42
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43 ret void
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44 }
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45
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46 ; GCN-LABEL: {{^}}store_build_vector_multiple_extract_uses_v4i32:
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47 ; GCN: buffer_load_dword
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48 ; GCN: buffer_load_dword
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49 ; GCN: buffer_load_dword
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50 ; GCN: buffer_load_dword
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51
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52 ; GCN: buffer_store_dwordx4
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53
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54 ; GCN: buffer_store_dword
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55 ; GCN: buffer_store_dword
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56 ; GCN: buffer_store_dword
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57 ; GCN: buffer_store_dword
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121
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58 define amdgpu_kernel void @store_build_vector_multiple_extract_uses_v4i32(<4 x i32> addrspace(1)* noalias %out0,
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120
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59 <4 x i32> addrspace(1)* noalias %out1,
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60 i32 addrspace(1)* noalias %out2,
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61 i32 addrspace(1)* %in) {
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62 %elt0 = load volatile i32, i32 addrspace(1)* %in
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63 %elt1 = load volatile i32, i32 addrspace(1)* %in
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64 %elt2 = load volatile i32, i32 addrspace(1)* %in
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65 %elt3 = load volatile i32, i32 addrspace(1)* %in
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66
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67 %vec0 = insertelement <4 x i32> undef, i32 %elt0, i32 0
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68 %vec1 = insertelement <4 x i32> %vec0, i32 %elt1, i32 1
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69 %vec2 = insertelement <4 x i32> %vec1, i32 %elt2, i32 2
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70 %vec3 = insertelement <4 x i32> %vec2, i32 %elt3, i32 3
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71
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72 %extract0 = extractelement <4 x i32> %vec3, i32 0
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73 %extract1 = extractelement <4 x i32> %vec3, i32 1
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74 %extract2 = extractelement <4 x i32> %vec3, i32 2
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75 %extract3 = extractelement <4 x i32> %vec3, i32 3
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76
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77 %op0 = add i32 %extract0, 3
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78 %op1 = sub i32 %extract1, 9
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79 %op2 = xor i32 %extract2, 1231412
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80 %op3 = and i32 %extract3, 258233412312
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81
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82 store <4 x i32> %vec3, <4 x i32> addrspace(1)* %out0
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83
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84 store volatile i32 %op0, i32 addrspace(1)* %out2
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85 store volatile i32 %op1, i32 addrspace(1)* %out2
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86 store volatile i32 %op2, i32 addrspace(1)* %out2
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87 store volatile i32 %op3, i32 addrspace(1)* %out2
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88
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89 ret void
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90 }
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91
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92 ; GCN-LABEL: {{^}}store_build_vector_multiple_uses_v4i32_bitcast_to_v2i64:
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93 ; GCN: buffer_load_dword
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94 ; GCN: buffer_load_dword
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95 ; GCN: buffer_load_dword
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96 ; GCN: buffer_load_dword
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97
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98 ; GCN: buffer_store_dwordx4
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99
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100 ; GCN: buffer_store_dwordx2
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101 ; GCN: buffer_store_dwordx2
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121
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102 define amdgpu_kernel void @store_build_vector_multiple_uses_v4i32_bitcast_to_v2i64(<2 x i64> addrspace(1)* noalias %out0,
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120
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103 <4 x i32> addrspace(1)* noalias %out1,
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104 i64 addrspace(1)* noalias %out2,
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105 i32 addrspace(1)* %in) {
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106 %elt0 = load volatile i32, i32 addrspace(1)* %in
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107 %elt1 = load volatile i32, i32 addrspace(1)* %in
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108 %elt2 = load volatile i32, i32 addrspace(1)* %in
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109 %elt3 = load volatile i32, i32 addrspace(1)* %in
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110
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111 %vec0 = insertelement <4 x i32> undef, i32 %elt0, i32 0
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112 %vec1 = insertelement <4 x i32> %vec0, i32 %elt1, i32 1
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113 %vec2 = insertelement <4 x i32> %vec1, i32 %elt2, i32 2
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114 %vec3 = insertelement <4 x i32> %vec2, i32 %elt3, i32 3
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115
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116 %bc.vec3 = bitcast <4 x i32> %vec3 to <2 x i64>
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117 store <2 x i64> %bc.vec3, <2 x i64> addrspace(1)* %out0
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118
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119 %extract0 = extractelement <2 x i64> %bc.vec3, i32 0
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120 %extract1 = extractelement <2 x i64> %bc.vec3, i32 1
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121
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122 store volatile i64 %extract0, i64 addrspace(1)* %out2
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123 store volatile i64 %extract1, i64 addrspace(1)* %out2
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124
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125 ret void
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126 }
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