annotate test/CodeGen/AMDGPU/fadd64.ll @ 128:c347d3398279 default tip

fix
author mir3636
date Wed, 06 Dec 2017 14:37:17 +0900
parents 803732b1fca8
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
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7d135dc70f03 LLVM 3.9
Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
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1 ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck %s
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Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
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2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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3
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Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
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4 ; CHECK-LABEL: {{^}}v_fadd_f64:
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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5 ; CHECK: v_add_f64 {{v[[0-9]+:[0-9]+]}}, {{v[[0-9]+:[0-9]+]}}, {{v[[0-9]+:[0-9]+]}}
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6 define amdgpu_kernel void @v_fadd_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
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parents: 95
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7 double addrspace(1)* %in2) {
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8 %tid = call i32 @llvm.amdgcn.workitem.id.x()
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9 %gep1 = getelementptr inbounds double, double addrspace(1)* %in1, i32 %tid
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10 %gep2 = getelementptr inbounds double, double addrspace(1)* %in2, i32 %tid
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11 %r0 = load double, double addrspace(1)* %gep1
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12 %r1 = load double, double addrspace(1)* %gep2
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7d135dc70f03 LLVM 3.9
Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
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13 %r2 = fadd double %r0, %r1
7d135dc70f03 LLVM 3.9
Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
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14 store double %r2, double addrspace(1)* %out
7d135dc70f03 LLVM 3.9
Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
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15 ret void
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Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
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16 }
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Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
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17
7d135dc70f03 LLVM 3.9
Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
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18 ; CHECK-LABEL: {{^}}s_fadd_f64:
121
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kono
parents: 100
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19 ; CHECK: v_add_f64 {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}
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20 define amdgpu_kernel void @s_fadd_f64(double addrspace(1)* %out, double %r0, double %r1) {
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7d135dc70f03 LLVM 3.9
Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
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21 %r2 = fadd double %r0, %r1
7d135dc70f03 LLVM 3.9
Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
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22 store double %r2, double addrspace(1)* %out
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Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
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23 ret void
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Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
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24 }
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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25
100
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Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
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26 ; CHECK-LABEL: {{^}}v_fadd_v2f64:
7d135dc70f03 LLVM 3.9
Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
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27 ; CHECK: v_add_f64
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Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
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28 ; CHECK: v_add_f64
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29 ; CHECK: _store_dwordx4
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30 define amdgpu_kernel void @v_fadd_v2f64(<2 x double> addrspace(1)* %out, <2 x double> addrspace(1)* %in1,
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Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
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31 <2 x double> addrspace(1)* %in2) {
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Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
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32 %r0 = load <2 x double>, <2 x double> addrspace(1)* %in1
7d135dc70f03 LLVM 3.9
Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
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33 %r1 = load <2 x double>, <2 x double> addrspace(1)* %in2
7d135dc70f03 LLVM 3.9
Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
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34 %r2 = fadd <2 x double> %r0, %r1
7d135dc70f03 LLVM 3.9
Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
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35 store <2 x double> %r2, <2 x double> addrspace(1)* %out
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Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
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36 ret void
95
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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37 }
100
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Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
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38
7d135dc70f03 LLVM 3.9
Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
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39 ; CHECK-LABEL: {{^}}s_fadd_v2f64:
7d135dc70f03 LLVM 3.9
Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
diff changeset
40 ; CHECK: v_add_f64 {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}
7d135dc70f03 LLVM 3.9
Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
diff changeset
41 ; CHECK: v_add_f64 {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}
121
803732b1fca8 LLVM 5.0
kono
parents: 100
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42 ; CHECK: _store_dwordx4
803732b1fca8 LLVM 5.0
kono
parents: 100
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43 define amdgpu_kernel void @s_fadd_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %r0, <2 x double> %r1) {
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7d135dc70f03 LLVM 3.9
Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
diff changeset
44 %r2 = fadd <2 x double> %r0, %r1
7d135dc70f03 LLVM 3.9
Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
diff changeset
45 store <2 x double> %r2, <2 x double> addrspace(1)* %out
7d135dc70f03 LLVM 3.9
Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
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46 ret void
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Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
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47 }
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48
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49 declare i32 @llvm.amdgcn.workitem.id.x() #1
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50
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51 attributes #0 = { nounwind }
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52 attributes #1 = { nounwind readnone }