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annotate test/CodeGen/AMDGPU/fmax3.f64.ll @ 128:c347d3398279 default tip

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fix
author mir3636
date Wed, 06 Dec 2017 14:37:17 +0900
parents 803732b1fca8
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1 ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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2 ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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4 declare double @llvm.maxnum.f64(double, double) nounwind readnone
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6 ; SI-LABEL: {{^}}test_fmax3_f64:
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7 ; SI-DAG: buffer_load_dwordx2 [[REGA:v\[[0-9]+:[0-9]+\]]], off, s[{{[0-9]+:[0-9]+}}], 0{{$}}
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8 ; SI-DAG: buffer_load_dwordx2 [[REGB:v\[[0-9]+:[0-9]+\]]], off, s[{{[0-9]+:[0-9]+}}], 0 offset:8
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9 ; SI: v_max_f64 [[REGA]], [[REGA]], [[REGB]]
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10 ; SI: buffer_load_dwordx2 [[REGC:v\[[0-9]+:[0-9]+\]]], off, s[{{[0-9]+:[0-9]+}}], 0 offset:16
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11 ; SI: v_max_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[REGA]], [[REGC]]
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12 ; SI: buffer_store_dwordx2 [[RESULT]],
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13 ; SI: s_endpgm
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14 define amdgpu_kernel void @test_fmax3_f64(double addrspace(1)* %out, double addrspace(1)* %aptr) nounwind {
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15 %bptr = getelementptr double, double addrspace(1)* %aptr, i32 1
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16 %cptr = getelementptr double, double addrspace(1)* %aptr, i32 2
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17 %a = load volatile double, double addrspace(1)* %aptr, align 8
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18 %b = load volatile double, double addrspace(1)* %bptr, align 8
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19 %c = load volatile double, double addrspace(1)* %cptr, align 8
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20 %f0 = call double @llvm.maxnum.f64(double %a, double %b) nounwind readnone
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21 %f1 = call double @llvm.maxnum.f64(double %f0, double %c) nounwind readnone
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22 store double %f1, double addrspace(1)* %out, align 8
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23 ret void
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24 }