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1 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SI %s
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2 ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI %s
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3 ; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9 %s
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4
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5 ; GCN-LABEL: {{^}}test_fmax3_olt_0_f32:
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6 ; GCN: buffer_load_dword [[REGC:v[0-9]+]]
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7 ; GCN: buffer_load_dword [[REGB:v[0-9]+]]
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8 ; GCN: buffer_load_dword [[REGA:v[0-9]+]]
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9 ; GCN: v_max3_f32 [[RESULT:v[0-9]+]], [[REGC]], [[REGB]], [[REGA]]
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10 ; GCN: buffer_store_dword [[RESULT]],
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11 ; GCN: s_endpgm
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12 define amdgpu_kernel void @test_fmax3_olt_0_f32(float addrspace(1)* %out, float addrspace(1)* %aptr, float addrspace(1)* %bptr, float addrspace(1)* %cptr) #0 {
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13 %a = load volatile float, float addrspace(1)* %aptr, align 4
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14 %b = load volatile float, float addrspace(1)* %bptr, align 4
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15 %c = load volatile float, float addrspace(1)* %cptr, align 4
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16 %f0 = call float @llvm.maxnum.f32(float %a, float %b)
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17 %f1 = call float @llvm.maxnum.f32(float %f0, float %c)
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18 store float %f1, float addrspace(1)* %out, align 4
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19 ret void
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20 }
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21
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22 ; Commute operand of second fmax
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23 ; GCN-LABEL: {{^}}test_fmax3_olt_1_f32:
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24 ; GCN: buffer_load_dword [[REGB:v[0-9]+]]
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25 ; GCN: buffer_load_dword [[REGA:v[0-9]+]]
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26 ; GCN: buffer_load_dword [[REGC:v[0-9]+]]
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27 ; GCN: v_max3_f32 [[RESULT:v[0-9]+]], [[REGC]], [[REGB]], [[REGA]]
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28 ; GCN: buffer_store_dword [[RESULT]],
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29 ; GCN: s_endpgm
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30 define amdgpu_kernel void @test_fmax3_olt_1_f32(float addrspace(1)* %out, float addrspace(1)* %aptr, float addrspace(1)* %bptr, float addrspace(1)* %cptr) #0 {
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31 %a = load volatile float, float addrspace(1)* %aptr, align 4
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32 %b = load volatile float, float addrspace(1)* %bptr, align 4
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33 %c = load volatile float, float addrspace(1)* %cptr, align 4
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34 %f0 = call float @llvm.maxnum.f32(float %a, float %b)
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35 %f1 = call float @llvm.maxnum.f32(float %c, float %f0)
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36 store float %f1, float addrspace(1)* %out, align 4
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37 ret void
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38 }
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39
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40 ; GCN-LABEL: {{^}}test_fmax3_olt_0_f16:
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41 ; GCN: buffer_load_ushort [[REGC:v[0-9]+]]
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42 ; GCN: buffer_load_ushort [[REGB:v[0-9]+]]
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43 ; GCN: buffer_load_ushort [[REGA:v[0-9]+]]
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44
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45 ; SI: v_max3_f32 [[RESULT_F32:v[0-9]+]],
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46 ; SI: v_cvt_f16_f32_e32 [[RESULT:v[0-9]+]], [[RESULT]]
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47
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48 ; VI: v_max_f16_e32
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49 ; VI: v_max_f16_e32 [[RESULT:v[0-9]+]],
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50
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51 ; GFX9: v_max3_f16 [[RESULT:v[0-9]+]], [[REGC]], [[REGB]], [[REGA]]
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52 ; GCN: buffer_store_short [[RESULT]],
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53 define amdgpu_kernel void @test_fmax3_olt_0_f16(half addrspace(1)* %out, half addrspace(1)* %aptr, half addrspace(1)* %bptr, half addrspace(1)* %cptr) #0 {
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54 %a = load volatile half, half addrspace(1)* %aptr, align 2
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55 %b = load volatile half, half addrspace(1)* %bptr, align 2
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56 %c = load volatile half, half addrspace(1)* %cptr, align 2
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57 %f0 = call half @llvm.maxnum.f16(half %a, half %b)
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58 %f1 = call half @llvm.maxnum.f16(half %f0, half %c)
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59 store half %f1, half addrspace(1)* %out, align 2
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60 ret void
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61 }
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62
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63 ; Commute operand of second fmax
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64 ; GCN-LABEL: {{^}}test_fmax3_olt_1_f16:
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65 ; GCN: buffer_load_ushort [[REGB:v[0-9]+]]
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66 ; GCN: buffer_load_ushort [[REGA:v[0-9]+]]
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67 ; GCN: buffer_load_ushort [[REGC:v[0-9]+]]
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68
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69 ; SI: v_max3_f32 [[RESULT_F32:v[0-9]+]],
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70 ; SI: v_cvt_f16_f32_e32 [[RESULT:v[0-9]+]], [[RESULT]]
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71
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72 ; VI: v_max_f16_e32
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73 ; VI: v_max_f16_e32 [[RESULT:v[0-9]+]],
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74
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75 ; GFX9: v_max3_f16 [[RESULT:v[0-9]+]], [[REGC]], [[REGB]], [[REGA]]
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76 ; GCN: buffer_store_short [[RESULT]],
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77 define amdgpu_kernel void @test_fmax3_olt_1_f16(half addrspace(1)* %out, half addrspace(1)* %aptr, half addrspace(1)* %bptr, half addrspace(1)* %cptr) #0 {
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78 %a = load volatile half, half addrspace(1)* %aptr, align 2
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79 %b = load volatile half, half addrspace(1)* %bptr, align 2
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80 %c = load volatile half, half addrspace(1)* %cptr, align 2
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81 %f0 = call half @llvm.maxnum.f16(half %a, half %b)
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82 %f1 = call half @llvm.maxnum.f16(half %c, half %f0)
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83 store half %f1, half addrspace(1)* %out, align 2
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84 ret void
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85 }
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86
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87 declare i32 @llvm.amdgcn.workitem.id.x() #1
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88 declare float @llvm.maxnum.f32(float, float) #1
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89 declare half @llvm.maxnum.f16(half, half) #1
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90
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91 attributes #0 = { nounwind }
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92 attributes #1 = { nounwind readnone speculatable }
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