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annotate test/CodeGen/AMDGPU/fmax_legacy.ll @ 128:c347d3398279 default tip

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fix
author mir3636
date Wed, 06 Dec 2017 14:37:17 +0900
parents 803732b1fca8
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
120
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1 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=SI-SAFE -check-prefix=FUNC %s
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2 ; RUN: llc -enable-no-nans-fp-math -enable-unsafe-fp-math -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI-NONAN -check-prefix=SI -check-prefix=FUNC %s
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3 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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4
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5 ; FIXME: Should replace unsafe-fp-math with no signed zeros.
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6
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7 declare i32 @llvm.r600.read.tidig.x() #1
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8
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9 ; FUNC-LABEL: @test_fmax_legacy_uge_f32
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10 ; SI: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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11 ; SI: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
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12 ; SI-SAFE: v_max_legacy_f32_e32 {{v[0-9]+}}, [[B]], [[A]]
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13 ; SI-NONAN: v_max_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
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14
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15 ; EG: MAX
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16 define amdgpu_kernel void @test_fmax_legacy_uge_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
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17 %tid = call i32 @llvm.r600.read.tidig.x() #1
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18 %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
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19 %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
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20
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21 %a = load volatile float, float addrspace(1)* %gep.0, align 4
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22 %b = load volatile float, float addrspace(1)* %gep.1, align 4
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23
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24 %cmp = fcmp uge float %a, %b
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25 %val = select i1 %cmp, float %a, float %b
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26 store float %val, float addrspace(1)* %out, align 4
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27 ret void
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28 }
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29
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30 ; FUNC-LABEL: @test_fmax_legacy_oge_f32
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31 ; SI: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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32 ; SI: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
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33 ; SI-SAFE: v_max_legacy_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
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34 ; SI-NONAN: v_max_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
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35 ; EG: MAX
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36 define amdgpu_kernel void @test_fmax_legacy_oge_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
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37 %tid = call i32 @llvm.r600.read.tidig.x() #1
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38 %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
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39 %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
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40
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41 %a = load volatile float, float addrspace(1)* %gep.0, align 4
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42 %b = load volatile float, float addrspace(1)* %gep.1, align 4
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43
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44 %cmp = fcmp oge float %a, %b
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45 %val = select i1 %cmp, float %a, float %b
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46 store float %val, float addrspace(1)* %out, align 4
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47 ret void
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48 }
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49
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50 ; FUNC-LABEL: @test_fmax_legacy_ugt_f32
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51 ; SI: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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52 ; SI: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
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53 ; SI-SAFE: v_max_legacy_f32_e32 {{v[0-9]+}}, [[B]], [[A]]
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54 ; SI-NONAN: v_max_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
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55 ; EG: MAX
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56 define amdgpu_kernel void @test_fmax_legacy_ugt_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
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57 %tid = call i32 @llvm.r600.read.tidig.x() #1
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58 %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
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59 %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
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60
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61 %a = load volatile float, float addrspace(1)* %gep.0, align 4
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62 %b = load volatile float, float addrspace(1)* %gep.1, align 4
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63
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64 %cmp = fcmp ugt float %a, %b
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65 %val = select i1 %cmp, float %a, float %b
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66 store float %val, float addrspace(1)* %out, align 4
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67 ret void
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68 }
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69
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70 ; FUNC-LABEL: @test_fmax_legacy_ogt_f32
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71 ; SI: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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72 ; SI: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
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73 ; SI-SAFE: v_max_legacy_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
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74 ; SI-NONAN: v_max_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
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75 ; EG: MAX
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76 define amdgpu_kernel void @test_fmax_legacy_ogt_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
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77 %tid = call i32 @llvm.r600.read.tidig.x() #1
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78 %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
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79 %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
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80
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81 %a = load volatile float, float addrspace(1)* %gep.0, align 4
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82 %b = load volatile float, float addrspace(1)* %gep.1, align 4
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83
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84 %cmp = fcmp ogt float %a, %b
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85 %val = select i1 %cmp, float %a, float %b
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86 store float %val, float addrspace(1)* %out, align 4
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87 ret void
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88 }
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89
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90 ; FUNC-LABEL: {{^}}test_fmax_legacy_ogt_v1f32:
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91 ; SI: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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92 ; SI: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
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93 ; SI-SAFE: v_max_legacy_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
121
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94 ; SI-NONAN: v_max_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
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95 ; EG: MAX
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96 define amdgpu_kernel void @test_fmax_legacy_ogt_v1f32(<1 x float> addrspace(1)* %out, <1 x float> addrspace(1)* %in) #0 {
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97 %tid = call i32 @llvm.r600.read.tidig.x() #1
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98 %gep.0 = getelementptr <1 x float>, <1 x float> addrspace(1)* %in, i32 %tid
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99 %gep.1 = getelementptr <1 x float>, <1 x float> addrspace(1)* %gep.0, i32 1
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100
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101 %a = load <1 x float>, <1 x float> addrspace(1)* %gep.0
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102 %b = load <1 x float>, <1 x float> addrspace(1)* %gep.1
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103
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104 %cmp = fcmp ogt <1 x float> %a, %b
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105 %val = select <1 x i1> %cmp, <1 x float> %a, <1 x float> %b
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106 store <1 x float> %val, <1 x float> addrspace(1)* %out
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107 ret void
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108 }
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109
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110 ; FUNC-LABEL: {{^}}test_fmax_legacy_ogt_v3f32:
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111 ; SI-SAFE: v_max_legacy_f32_e32
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112 ; SI-SAFE: v_max_legacy_f32_e32
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113 ; SI-SAFE: v_max_legacy_f32_e32
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114 ; SI-NONAN: v_max_f32_e32
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115 ; SI-NONAN: v_max_f32_e32
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116 ; SI-NONAN: v_max_f32_e32
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117 define amdgpu_kernel void @test_fmax_legacy_ogt_v3f32(<3 x float> addrspace(1)* %out, <3 x float> addrspace(1)* %in) #0 {
100
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118 %tid = call i32 @llvm.r600.read.tidig.x() #1
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119 %gep.0 = getelementptr <3 x float>, <3 x float> addrspace(1)* %in, i32 %tid
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120 %gep.1 = getelementptr <3 x float>, <3 x float> addrspace(1)* %gep.0, i32 1
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121
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122 %a = load <3 x float>, <3 x float> addrspace(1)* %gep.0
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123 %b = load <3 x float>, <3 x float> addrspace(1)* %gep.1
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124
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125 %cmp = fcmp ogt <3 x float> %a, %b
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126 %val = select <3 x i1> %cmp, <3 x float> %a, <3 x float> %b
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127 store <3 x float> %val, <3 x float> addrspace(1)* %out
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128 ret void
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129 }
95
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130
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131 ; FUNC-LABEL: @test_fmax_legacy_ogt_f32_multi_use
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132 ; SI: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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133 ; SI: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
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134 ; SI-NOT: v_max_
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135 ; SI: v_cmp_gt_f32
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136 ; SI-NEXT: v_cndmask_b32
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137 ; SI-NOT: v_max_
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138
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139 ; EG: MAX
121
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140 define amdgpu_kernel void @test_fmax_legacy_ogt_f32_multi_use(float addrspace(1)* %out0, i1 addrspace(1)* %out1, float addrspace(1)* %in) #0 {
95
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141 %tid = call i32 @llvm.r600.read.tidig.x() #1
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142 %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
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143 %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
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144
120
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145 %a = load volatile float, float addrspace(1)* %gep.0, align 4
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146 %b = load volatile float, float addrspace(1)* %gep.1, align 4
95
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147
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148 %cmp = fcmp ogt float %a, %b
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149 %val = select i1 %cmp, float %a, float %b
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150 store float %val, float addrspace(1)* %out0, align 4
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151 store i1 %cmp, i1addrspace(1)* %out1
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152 ret void
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153 }
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154
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155 attributes #0 = { nounwind }
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156 attributes #1 = { nounwind readnone }