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121
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1 ; RUN: llc -amdgpu-scalarize-global-loads=false -verify-machineinstrs -mcpu=tahiti -mattr=-fp32-denormals,+fast-fmaf -fp-contract=on < %s | FileCheck -check-prefixes=GCN,GCN-FLUSH-STRICT,GCN-FLUSH,SI-FLUSH,GCN-FLUSH-FASTFMA,GCN-FLUSH-FASTFMA-STRICT,SI %s
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2 ; RUN: llc -amdgpu-scalarize-global-loads=false -verify-machineinstrs -mcpu=tahiti -mattr=+fp32-denormals,+fast-fmaf -fp-contract=on < %s | FileCheck -check-prefixes=GCN,GCN-DENORM-STRICT,GCN-DENORM,SI-DENORM,GCN-DENORM-FASTFMA,GCN-DENORM-FASTFMA-STRICT,SI %s
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3 ; RUN: llc -amdgpu-scalarize-global-loads=false -verify-machineinstrs -mcpu=verde -mattr=-fp32-denormals,-fast-fmaf -fp-contract=on < %s | FileCheck -check-prefixes=GCN,GCN-FLUSH-STRICT,GCN-FLUSH,SI-FLUSH,GCN-FLUSH-SLOWFMA,GCN-FLUSH-SLOWFMA-STRICT,SI %s
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4 ; RUN: llc -amdgpu-scalarize-global-loads=false -verify-machineinstrs -mcpu=verde -mattr=+fp32-denormals,-fast-fmaf -fp-contract=on < %s | FileCheck -check-prefixes=GCN,GCN-DENORM-STRICT,GCN-DENORM,SI-DENORM,GCN-DENORM-SLOWFMA,GCN-DENORM-SLOWFMA-STRICT,SI %s
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5
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6 ; RUN: llc -amdgpu-scalarize-global-loads=false -verify-machineinstrs -mcpu=tahiti -mattr=-fp32-denormals,+fast-fmaf -fp-contract=fast < %s | FileCheck -check-prefixes=GCN,GCN-FLUSH-CONTRACT,GCN-FLUSH,SI-FLUSH,GCN-FLUSH-FASTFMA,GCN-FLUSH-FASTFMA-CONTRACT,SI %s
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7 ; RUN: llc -amdgpu-scalarize-global-loads=false -verify-machineinstrs -mcpu=tahiti -mattr=+fp32-denormals,+fast-fmaf -fp-contract=fast < %s | FileCheck -check-prefixes=GCN,GCN-DENORM-CONTRACT,GCN-DENORM,SI-DENORM,GCN-DENORM-FASTFMA,GCN-DENORM-FASTFMA-CONTRACT,SI %s
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8 ; RUN: llc -amdgpu-scalarize-global-loads=false -verify-machineinstrs -mcpu=verde -mattr=-fp32-denormals,-fast-fmaf -fp-contract=fast < %s | FileCheck -check-prefixes=GCN,GCN-FLUSH-CONTRACT,GCN-FLUSH,SI-FLUSH,GCN-FLUSH-SLOWFMA,GCN-FLUSH-SLOWFMA-CONTRACT,SI %s
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9 ; RUN: llc -amdgpu-scalarize-global-loads=false -verify-machineinstrs -mcpu=verde -mattr=+fp32-denormals,-fast-fmaf -fp-contract=fast < %s | FileCheck -check-prefixes=GCN,GCN-DENORM-CONTRACT,GCN-DENORM,SI-DENORM,GCN-DENORM-SLOWFMA,GCN-DENORM-SLOWFMA-CONTRACT,SI %s
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10
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11 ; Test all permutations of: fp32 denormals, fast fp contract, fp contract enabled for fmuladd, fmaf fast/slow.
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12
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13 target triple = "amdgcn--"
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14
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15
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16 declare i32 @llvm.amdgcn.workitem.id.x() #1
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17 declare float @llvm.fmuladd.f32(float, float, float) #1
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18 declare half @llvm.fmuladd.f16(half, half, half) #1
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19 declare float @llvm.fabs.f32(float) #1
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20
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21 ; GCN-LABEL: {{^}}fmuladd_f32:
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22 ; GCN-FLUSH: v_mac_f32_e32 {{v[0-9]+, v[0-9]+, v[0-9]+}}
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23
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24 ; GCN-DENORM-FASTFMA: v_fma_f32 {{v[0-9]+, v[0-9]+, v[0-9]+}}
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25
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26 ; GCN-DENORM-SLOWFMA: v_mul_f32_e32 {{v[0-9]+, v[0-9]+, v[0-9]+}}
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27 ; GCN-DENORM-SLOWFMA: v_add_f32_e32 {{v[0-9]+, v[0-9]+, v[0-9]+}}
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28 define amdgpu_kernel void @fmuladd_f32(float addrspace(1)* %out, float addrspace(1)* %in1,
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29 float addrspace(1)* %in2, float addrspace(1)* %in3) #0 {
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30 %r0 = load float, float addrspace(1)* %in1
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31 %r1 = load float, float addrspace(1)* %in2
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32 %r2 = load float, float addrspace(1)* %in3
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33 %r3 = tail call float @llvm.fmuladd.f32(float %r0, float %r1, float %r2)
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34 store float %r3, float addrspace(1)* %out
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35 ret void
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36 }
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37
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38 ; GCN-LABEL: {{^}}fmul_fadd_f32:
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39 ; GCN-FLUSH: v_mac_f32
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40
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41 ; GCN-DENORM-FASTFMA-CONTRACT: v_fma_f32
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42
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43 ; GCN-DENORM-SLOWFMA-CONTRACT: v_mul_f32_e32
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44 ; GCN-DENORM-SLOWFMA-CONTRACT: v_add_f32_e32
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45
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46 ; GCN-DENORM-STRICT: v_mul_f32_e32
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47 ; GCN-DENORM-STRICT: v_add_f32_e32
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48 define amdgpu_kernel void @fmul_fadd_f32(float addrspace(1)* %out, float addrspace(1)* %in1,
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49 float addrspace(1)* %in2, float addrspace(1)* %in3) #0 {
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50 %r0 = load volatile float, float addrspace(1)* %in1
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51 %r1 = load volatile float, float addrspace(1)* %in2
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52 %r2 = load volatile float, float addrspace(1)* %in3
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53 %mul = fmul float %r0, %r1
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54 %add = fadd float %mul, %r2
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55 store float %add, float addrspace(1)* %out
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56 ret void
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57 }
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58
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59 ; GCN-LABEL: {{^}}fmuladd_2.0_a_b_f32
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60 ; GCN: {{buffer|flat}}_load_dword [[R1:v[0-9]+]],
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61 ; GCN: {{buffer|flat}}_load_dword [[R2:v[0-9]+]],
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62
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63 ; GCN-FLUSH: v_mac_f32_e32 [[R2]], 2.0, [[R1]]
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64 ; SI-FLUSH: buffer_store_dword [[R2]]
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65 ; VI-FLUSH: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[R2]]
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66
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67 ; GCN-DENORM-FASTFMA: v_fma_f32 [[RESULT:v[0-9]+]], [[R1]], 2.0, [[R2]]
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68
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69 ; GCN-DENORM-SLOWFMA: v_add_f32_e32 [[TMP:v[0-9]+]], [[R1]], [[R1]]
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70 ; GCN-DENORM-SLOWFMA: v_add_f32_e32 [[RESULT:v[0-9]+]], [[TMP]], [[R2]]
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71
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72 ; SI-DENORM buffer_store_dword [[RESULT]]
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73 ; VI-DENORM: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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74 define amdgpu_kernel void @fmuladd_2.0_a_b_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
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75 %tid = call i32 @llvm.amdgcn.workitem.id.x()
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76 %gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
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77 %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
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78 %gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid
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79
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80 %r1 = load volatile float, float addrspace(1)* %gep.0
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81 %r2 = load volatile float, float addrspace(1)* %gep.1
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82
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83 %r3 = tail call float @llvm.fmuladd.f32(float 2.0, float %r1, float %r2)
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84 store float %r3, float addrspace(1)* %gep.out
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85 ret void
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86 }
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87
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88 ; GCN-LABEL: {{^}}fmuladd_a_2.0_b_f32
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89 ; GCN: {{buffer|flat}}_load_dword [[R1:v[0-9]+]],
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90 ; GCN: {{buffer|flat}}_load_dword [[R2:v[0-9]+]],
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91
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92 ; GCN-FLUSH: v_mac_f32_e32 [[R2]], 2.0, [[R1]]
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93 ; SI-FLUSH: buffer_store_dword [[R2]]
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94 ; VI-FLUSH: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[R2]]
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95
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96 ; GCN-DENORM-FASTFMA: v_fma_f32 [[RESULT:v[0-9]+]], [[R1]], 2.0, [[R2]]
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97
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98 ; GCN-DENORM-SLOWFMA: v_add_f32_e32 [[TMP:v[0-9]+]], [[R1]], [[R1]]
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99 ; GCN-DENORM-SLOWFMA: v_add_f32_e32 [[RESULT:v[0-9]+]], [[TMP]], [[R2]]
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100
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101 ; SI-DENORM: buffer_store_dword [[RESULT]]
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102 ; VI-DENORM: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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103 define amdgpu_kernel void @fmuladd_a_2.0_b_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
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104 %tid = call i32 @llvm.amdgcn.workitem.id.x()
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105 %gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
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106 %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
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107 %gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid
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108
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109 %r1 = load volatile float, float addrspace(1)* %gep.0
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110 %r2 = load volatile float, float addrspace(1)* %gep.1
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111
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112 %r3 = tail call float @llvm.fmuladd.f32(float %r1, float 2.0, float %r2)
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113 store float %r3, float addrspace(1)* %gep.out
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114 ret void
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115 }
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116
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117 ; GCN-LABEL: {{^}}fadd_a_a_b_f32:
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118 ; GCN: {{buffer|flat}}_load_dword [[R1:v[0-9]+]],
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119 ; GCN: {{buffer|flat}}_load_dword [[R2:v[0-9]+]],
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120
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121 ; GCN-FLUSH: v_mac_f32_e32 [[R2]], 2.0, [[R1]]
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122 ; SI-FLUSH: buffer_store_dword [[R2]]
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123 ; VI-FLUSH: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[R2]]
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124
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125 ; GCN-DENORM-FASTFMA-CONTRACT: v_fma_f32 [[RESULT:v[0-9]+]], [[R1]], 2.0, [[R2]]
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126
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127 ; GCN-DENORM-SLOWFMA-CONTRACT: v_add_f32_e32 [[TMP:v[0-9]+]], [[R1]], [[R1]]
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128 ; GCN-DENORM-SLOWFMA-CONTRACT: v_add_f32_e32 [[RESULT:v[0-9]+]], [[TMP]], [[R2]]
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129
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130 ; GCN-DENORM-STRICT: v_add_f32_e32 [[TMP:v[0-9]+]], [[R1]], [[R1]]
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131 ; GCN-DENORM-STRICT: v_add_f32_e32 [[RESULT:v[0-9]+]], [[TMP]], [[R2]]
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132
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133 ; SI-DENORM: buffer_store_dword [[RESULT]]
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134 ; VI-DENORM: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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135 define amdgpu_kernel void @fadd_a_a_b_f32(float addrspace(1)* %out,
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136 float addrspace(1)* %in1,
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137 float addrspace(1)* %in2) #0 {
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138 %tid = call i32 @llvm.amdgcn.workitem.id.x()
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139 %gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
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140 %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
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141 %gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid
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142
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143 %r0 = load volatile float, float addrspace(1)* %gep.0
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144 %r1 = load volatile float, float addrspace(1)* %gep.1
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145
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146 %add.0 = fadd float %r0, %r0
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147 %add.1 = fadd float %add.0, %r1
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148 store float %add.1, float addrspace(1)* %gep.out
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149 ret void
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150 }
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151
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152 ; GCN-LABEL: {{^}}fadd_b_a_a_f32:
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153 ; GCN: {{buffer|flat}}_load_dword [[R1:v[0-9]+]],
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154 ; GCN: {{buffer|flat}}_load_dword [[R2:v[0-9]+]],
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155
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156 ; GCN-FLUSH: v_mac_f32_e32 [[R2]], 2.0, [[R1]]
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157 ; SI-FLUSH: buffer_store_dword [[R2]]
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158 ; VI-FLUSH: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[R2]]
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159
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160 ; GCN-DENORM-FASTFMA-CONTRACT: v_fma_f32 [[RESULT:v[0-9]+]], [[R1]], 2.0, [[R2]]
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161
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162 ; GCN-DENORM-SLOWFMA-CONTRACT: v_add_f32_e32 [[TMP:v[0-9]+]], [[R1]], [[R1]]
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163 ; GCN-DENORM-SLOWFMA-CONTRACT: v_add_f32_e32 [[RESULT:v[0-9]+]], [[R2]], [[TMP]]
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164
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165 ; GCN-DENORM-STRICT: v_add_f32_e32 [[TMP:v[0-9]+]], [[R1]], [[R1]]
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166 ; GCN-DENORM-STRICT: v_add_f32_e32 [[RESULT:v[0-9]+]], [[R2]], [[TMP]]
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167
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168 ; SI-DENORM: buffer_store_dword [[RESULT]]
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169 ; VI-DENORM: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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170 define amdgpu_kernel void @fadd_b_a_a_f32(float addrspace(1)* %out,
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171 float addrspace(1)* %in1,
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172 float addrspace(1)* %in2) #0 {
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173 %tid = call i32 @llvm.amdgcn.workitem.id.x()
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174 %gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
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175 %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
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176 %gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid
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177
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178 %r0 = load volatile float, float addrspace(1)* %gep.0
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179 %r1 = load volatile float, float addrspace(1)* %gep.1
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180
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181 %add.0 = fadd float %r0, %r0
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182 %add.1 = fadd float %r1, %add.0
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183 store float %add.1, float addrspace(1)* %gep.out
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184 ret void
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185 }
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186
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187 ; GCN-LABEL: {{^}}fmuladd_neg_2.0_a_b_f32
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188 ; GCN: {{buffer|flat}}_load_dword [[R1:v[0-9]+]],
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189 ; GCN: {{buffer|flat}}_load_dword [[R2:v[0-9]+]],
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190 ; GCN-FLUSH: v_mac_f32_e32 [[R2]], -2.0, [[R1]]
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191
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192 ; GCN-DENORM-FASTFMA: v_fma_f32 [[RESULT:v[0-9]+]], [[R1]], -2.0, [[R2]]
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193
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194 ; GCN-DENORM-SLOWFMA: v_add_f32_e32 [[TMP:v[0-9]+]], [[R1]], [[R1]]
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195 ; GCN-DENORM-SLOWFMA: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[R2]], [[TMP]]
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196
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197 ; SI-DENORM: buffer_store_dword [[RESULT]]
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198 ; VI-DENORM: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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199 define amdgpu_kernel void @fmuladd_neg_2.0_a_b_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
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200 %tid = call i32 @llvm.amdgcn.workitem.id.x()
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201 %gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
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202 %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
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203 %gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid
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204
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205 %r1 = load volatile float, float addrspace(1)* %gep.0
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206 %r2 = load volatile float, float addrspace(1)* %gep.1
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207
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208 %r3 = tail call float @llvm.fmuladd.f32(float -2.0, float %r1, float %r2)
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209 store float %r3, float addrspace(1)* %gep.out
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210 ret void
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211 }
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212
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213 ; GCN-LABEL: {{^}}fmuladd_neg_2.0_neg_a_b_f32
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214 ; GCN: {{buffer|flat}}_load_dword [[R1:v[0-9]+]],
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215 ; GCN: {{buffer|flat}}_load_dword [[R2:v[0-9]+]],
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216
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217 ; GCN-FLUSH: v_mac_f32_e32 [[R2]], 2.0, [[R1]]
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218 ; SI-FLUSH: buffer_store_dword [[R2]]
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219 ; VI-FLUSH: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[R2]]
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220
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221 ; GCN-DENORM-FASTFMA: v_fma_f32 [[RESULT:v[0-9]+]], -[[R1]], -2.0, [[R2]]
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222
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223 ; GCN-DENORM-SLOWFMA: v_add_f32_e32 [[TMP:v[0-9]+]], [[R1]], [[R1]]
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224 ; GCN-DENORM-SLOWFMA: v_add_f32_e32 [[RESULT:v[0-9]+]], [[R2]], [[TMP]]
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225
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226 ; SI-DENORM: buffer_store_dword [[RESULT]]
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227 ; VI-DENORM: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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228 define amdgpu_kernel void @fmuladd_neg_2.0_neg_a_b_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
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229 %tid = call i32 @llvm.amdgcn.workitem.id.x()
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230 %gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
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231 %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
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232 %gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid
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233
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234 %r1 = load volatile float, float addrspace(1)* %gep.0
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235 %r2 = load volatile float, float addrspace(1)* %gep.1
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236
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237 %r1.fneg = fsub float -0.000000e+00, %r1
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238
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239 %r3 = tail call float @llvm.fmuladd.f32(float -2.0, float %r1.fneg, float %r2)
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240 store float %r3, float addrspace(1)* %gep.out
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241 ret void
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242 }
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243
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244 ; GCN-LABEL: {{^}}fmuladd_2.0_neg_a_b_f32:
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245 ; GCN: {{buffer|flat}}_load_dword [[R1:v[0-9]+]],
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246 ; GCN: {{buffer|flat}}_load_dword [[R2:v[0-9]+]],
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247
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248 ; GCN-FLUSH: v_mac_f32_e32 [[R2]], -2.0, [[R1]]
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249 ; SI-FLUSH: buffer_store_dword [[R2]]
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250 ; VI-FLUSH: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[R2]]
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251
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252 ; GCN-DENORM-FASTFMA: v_fma_f32 [[RESULT:v[0-9]+]], -[[R1]], 2.0, [[R2]]
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253
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254 ; GCN-DENORM-SLOWFMA: v_add_f32_e32 [[TMP:v[0-9]+]], [[R1]], [[R1]]
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255 ; GCN-DENORM-SLOWFMA: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[R2]], [[TMP]]
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256
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257 ; SI-DENORM: buffer_store_dword [[RESULT]]
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258 ; VI-DENORM: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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259 define amdgpu_kernel void @fmuladd_2.0_neg_a_b_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
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260 %tid = call i32 @llvm.amdgcn.workitem.id.x()
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261 %gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
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262 %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
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263 %gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid
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264
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265 %r1 = load volatile float, float addrspace(1)* %gep.0
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266 %r2 = load volatile float, float addrspace(1)* %gep.1
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267
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268 %r1.fneg = fsub float -0.000000e+00, %r1
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269
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270 %r3 = tail call float @llvm.fmuladd.f32(float 2.0, float %r1.fneg, float %r2)
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271 store float %r3, float addrspace(1)* %gep.out
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272 ret void
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273 }
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274
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275 ; GCN-LABEL: {{^}}fmuladd_2.0_a_neg_b_f32:
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276 ; GCN: {{buffer|flat}}_load_dword [[R1:v[0-9]+]],
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277 ; GCN: {{buffer|flat}}_load_dword [[R2:v[0-9]+]],
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278 ; GCN-FLUSH: v_mad_f32 [[RESULT:v[0-9]+]], [[R1]], 2.0, -[[R2]]
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279 ; SI-FLUSH: buffer_store_dword [[RESULT]]
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280 ; VI-FLUSH: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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281
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282 ; GCN-DENORM-FASTFMA: v_fma_f32 [[RESULT:v[0-9]+]], [[R1]], 2.0, -[[R2]]
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283
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284 ; GCN-DENORM-SLOWFMA: v_add_f32_e32 [[TMP:v[0-9]+]], [[R1]], [[R1]]
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285 ; GCN-DENORM-SLOWFMA: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[TMP]], [[R2]]
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286
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287 ; SI-DENORM: buffer_store_dword [[RESULT]]
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288 ; VI-DENORM: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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289 define amdgpu_kernel void @fmuladd_2.0_a_neg_b_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
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290 %tid = call i32 @llvm.amdgcn.workitem.id.x()
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291 %gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
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292 %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
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293 %gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid
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294
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295 %r1 = load volatile float, float addrspace(1)* %gep.0
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296 %r2 = load volatile float, float addrspace(1)* %gep.1
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297
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298 %r2.fneg = fsub float -0.000000e+00, %r2
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299
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300 %r3 = tail call float @llvm.fmuladd.f32(float 2.0, float %r1, float %r2.fneg)
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301 store float %r3, float addrspace(1)* %gep.out
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302 ret void
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303 }
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304
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305 ; GCN-LABEL: {{^}}mad_sub_f32:
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306 ; GCN: {{buffer|flat}}_load_dword [[REGA:v[0-9]+]]
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307 ; GCN: {{buffer|flat}}_load_dword [[REGB:v[0-9]+]]
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308 ; GCN: {{buffer|flat}}_load_dword [[REGC:v[0-9]+]]
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309 ; GCN-FLUSH: v_mad_f32 [[RESULT:v[0-9]+]], [[REGA]], [[REGB]], -[[REGC]]
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310
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311 ; GCN-DENORM-FASTFMA-CONTRACT: v_fma_f32 [[RESULT:v[0-9]+]], [[REGA]], [[REGB]], -[[REGC]]
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312
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313 ; GCN-DENORM-SLOWFMA-CONTRACT: v_mul_f32_e32 [[TMP:v[0-9]+]], [[REGA]], [[REGB]]
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314 ; GCN-DENORM-SLOWFMA-CONTRACT: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[TMP]], [[REGC]]
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315
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316 ; GCN-DENORM-STRICT: v_mul_f32_e32 [[TMP:v[0-9]+]], [[REGA]], [[REGB]]
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317 ; GCN-DENORM-STRICT: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[TMP]], [[REGC]]
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318
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319 ; SI: buffer_store_dword [[RESULT]]
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320 ; VI: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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321 define amdgpu_kernel void @mad_sub_f32(float addrspace(1)* noalias nocapture %out, float addrspace(1)* noalias nocapture readonly %ptr) #0 {
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322 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0
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323 %tid.ext = sext i32 %tid to i64
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324 %gep0 = getelementptr float, float addrspace(1)* %ptr, i64 %tid.ext
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325 %add1 = add i64 %tid.ext, 1
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326 %gep1 = getelementptr float, float addrspace(1)* %ptr, i64 %add1
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327 %add2 = add i64 %tid.ext, 2
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328 %gep2 = getelementptr float, float addrspace(1)* %ptr, i64 %add2
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329 %outgep = getelementptr float, float addrspace(1)* %out, i64 %tid.ext
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330 %a = load volatile float, float addrspace(1)* %gep0, align 4
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331 %b = load volatile float, float addrspace(1)* %gep1, align 4
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332 %c = load volatile float, float addrspace(1)* %gep2, align 4
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333 %mul = fmul float %a, %b
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334 %sub = fsub float %mul, %c
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335 store float %sub, float addrspace(1)* %outgep, align 4
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336 ret void
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|
337 }
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338
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339 ; GCN-LABEL: {{^}}mad_sub_inv_f32:
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340 ; GCN: {{buffer|flat}}_load_dword [[REGA:v[0-9]+]]
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341 ; GCN: {{buffer|flat}}_load_dword [[REGB:v[0-9]+]]
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342 ; GCN: {{buffer|flat}}_load_dword [[REGC:v[0-9]+]]
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343
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344 ; GCN-FLUSH: v_mad_f32 [[RESULT:v[0-9]+]], -[[REGA]], [[REGB]], [[REGC]]
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345
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346 ; GCN-DENORM-FASTFMA-CONTRACT: v_fma_f32 [[RESULT:v[0-9]+]], -[[REGA]], [[REGB]], [[REGC]]
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347
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348 ; GCN-DENORM-SLOWFMA-CONTRACT: v_mul_f32_e32 [[TMP:v[0-9]+]], [[REGA]], [[REGB]]
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349 ; GCN-DENORM-SLOWFMA-CONTRACT: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[REGC]], [[TMP]]
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350
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351 ; GCN-DENORM-STRICT: v_mul_f32_e32 [[TMP:v[0-9]+]], [[REGA]], [[REGB]]
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352 ; GCN-DENORM-STRICT: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[REGC]], [[TMP]]
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353
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354 ; SI: buffer_store_dword [[RESULT]]
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355 ; VI: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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356 define amdgpu_kernel void @mad_sub_inv_f32(float addrspace(1)* noalias nocapture %out, float addrspace(1)* noalias nocapture readonly %ptr) #0 {
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357 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0
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358 %tid.ext = sext i32 %tid to i64
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359 %gep0 = getelementptr float, float addrspace(1)* %ptr, i64 %tid.ext
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360 %add1 = add i64 %tid.ext, 1
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361 %gep1 = getelementptr float, float addrspace(1)* %ptr, i64 %add1
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362 %add2 = add i64 %tid.ext, 2
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363 %gep2 = getelementptr float, float addrspace(1)* %ptr, i64 %add2
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364 %outgep = getelementptr float, float addrspace(1)* %out, i64 %tid.ext
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365 %a = load volatile float, float addrspace(1)* %gep0, align 4
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366 %b = load volatile float, float addrspace(1)* %gep1, align 4
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367 %c = load volatile float, float addrspace(1)* %gep2, align 4
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368 %mul = fmul float %a, %b
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369 %sub = fsub float %c, %mul
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|
|
370 store float %sub, float addrspace(1)* %outgep, align 4
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|
|
371 ret void
|
|
|
372 }
|
|
|
373
|
|
|
374 ; GCN-LABEL: {{^}}mad_sub_fabs_f32:
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|
375 ; GCN: {{buffer|flat}}_load_dword [[REGA:v[0-9]+]]
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|
|
376 ; GCN: {{buffer|flat}}_load_dword [[REGB:v[0-9]+]]
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|
377 ; GCN: {{buffer|flat}}_load_dword [[REGC:v[0-9]+]]
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|
378 ; GCN-FLUSH: v_mad_f32 [[RESULT:v[0-9]+]], [[REGA]], [[REGB]], -|[[REGC]]|
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|
|
379
|
|
|
380 ; GCN-DENORM-FASTFMA-CONTRACT: v_fma_f32 [[RESULT:v[0-9]+]], [[REGA]], [[REGB]], -|[[REGC]]|
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|
|
381
|
|
|
382 ; GCN-DENORM-SLOWFMA-CONTRACT: v_mul_f32_e32 [[TMP:v[0-9]+]], [[REGA]], [[REGB]]
|
|
|
383 ; GCN-DENORM-SLOWFMA-CONTRACT: v_sub_f32_e64 [[RESULT:v[0-9]+]], [[TMP]], |[[REGC]]|
|
|
|
384
|
|
|
385 ; GCN-DENORM-STRICT: v_mul_f32_e32 [[TMP:v[0-9]+]], [[REGA]], [[REGB]]
|
|
|
386 ; GCN-DENORM-STRICT: v_sub_f32_e64 [[RESULT:v[0-9]+]], [[TMP]], |[[REGC]]|
|
|
|
387
|
|
|
388 ; SI: buffer_store_dword [[RESULT]]
|
|
|
389 ; VI: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
|
|
|
390 define amdgpu_kernel void @mad_sub_fabs_f32(float addrspace(1)* noalias nocapture %out, float addrspace(1)* noalias nocapture readonly %ptr) #0 {
|
|
|
391 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0
|
|
|
392 %tid.ext = sext i32 %tid to i64
|
|
|
393 %gep0 = getelementptr float, float addrspace(1)* %ptr, i64 %tid.ext
|
|
|
394 %add1 = add i64 %tid.ext, 1
|
|
|
395 %gep1 = getelementptr float, float addrspace(1)* %ptr, i64 %add1
|
|
|
396 %add2 = add i64 %tid.ext, 2
|
|
|
397 %gep2 = getelementptr float, float addrspace(1)* %ptr, i64 %add2
|
|
|
398 %outgep = getelementptr float, float addrspace(1)* %out, i64 %tid.ext
|
|
|
399 %a = load volatile float, float addrspace(1)* %gep0, align 4
|
|
|
400 %b = load volatile float, float addrspace(1)* %gep1, align 4
|
|
|
401 %c = load volatile float, float addrspace(1)* %gep2, align 4
|
|
|
402 %c.abs = call float @llvm.fabs.f32(float %c) #0
|
|
|
403 %mul = fmul float %a, %b
|
|
|
404 %sub = fsub float %mul, %c.abs
|
|
|
405 store float %sub, float addrspace(1)* %outgep, align 4
|
|
|
406 ret void
|
|
|
407 }
|
|
|
408
|
|
|
409 ; GCN-LABEL: {{^}}mad_sub_fabs_inv_f32:
|
|
|
410 ; GCN: {{buffer|flat}}_load_dword [[REGA:v[0-9]+]]
|
|
|
411 ; GCN: {{buffer|flat}}_load_dword [[REGB:v[0-9]+]]
|
|
|
412 ; GCN: {{buffer|flat}}_load_dword [[REGC:v[0-9]+]]
|
|
|
413 ; GCN-FLUSH: v_mad_f32 [[RESULT:v[0-9]+]], -[[REGA]], [[REGB]], |[[REGC]]|
|
|
|
414
|
|
|
415 ; GCN-DENORM-FASTFMA-CONTRACT: v_fma_f32 [[RESULT:v[0-9]+]], -[[REGA]], [[REGB]], |[[REGC]]|
|
|
|
416
|
|
|
417 ; GCN-DENORM-SLOWFMA-CONTRACT: v_mul_f32_e32 [[TMP:v[0-9]+]], [[REGA]], [[REGB]]
|
|
|
418 ; GCN-DENORM-SLOWFMA-CONTRACT: v_sub_f32_e64 [[RESULT:v[0-9]+]], |[[REGC]]|, [[TMP]]
|
|
|
419
|
|
|
420 ; GCN-DENORM-STRICT: v_mul_f32_e32 [[TMP:v[0-9]+]], [[REGA]], [[REGB]]
|
|
|
421 ; GCN-DENORM-STRICT: v_sub_f32_e64 [[RESULT:v[0-9]+]], |[[REGC]]|, [[TMP]]
|
|
|
422
|
|
|
423 ; SI: buffer_store_dword [[RESULT]]
|
|
|
424 ; VI: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
|
|
|
425 define amdgpu_kernel void @mad_sub_fabs_inv_f32(float addrspace(1)* noalias nocapture %out, float addrspace(1)* noalias nocapture readonly %ptr) #0 {
|
|
|
426 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0
|
|
|
427 %tid.ext = sext i32 %tid to i64
|
|
|
428 %gep0 = getelementptr float, float addrspace(1)* %ptr, i64 %tid.ext
|
|
|
429 %add1 = add i64 %tid.ext, 1
|
|
|
430 %gep1 = getelementptr float, float addrspace(1)* %ptr, i64 %add1
|
|
|
431 %add2 = add i64 %tid.ext, 2
|
|
|
432 %gep2 = getelementptr float, float addrspace(1)* %ptr, i64 %add2
|
|
|
433 %outgep = getelementptr float, float addrspace(1)* %out, i64 %tid.ext
|
|
|
434 %a = load volatile float, float addrspace(1)* %gep0, align 4
|
|
|
435 %b = load volatile float, float addrspace(1)* %gep1, align 4
|
|
|
436 %c = load volatile float, float addrspace(1)* %gep2, align 4
|
|
|
437 %c.abs = call float @llvm.fabs.f32(float %c) #0
|
|
|
438 %mul = fmul float %a, %b
|
|
|
439 %sub = fsub float %c.abs, %mul
|
|
|
440 store float %sub, float addrspace(1)* %outgep, align 4
|
|
|
441 ret void
|
|
|
442 }
|
|
|
443
|
|
|
444 ; GCN-LABEL: {{^}}neg_neg_mad_f32:
|
|
|
445 ; GCN: {{buffer|flat}}_load_dword [[REGA:v[0-9]+]]
|
|
|
446 ; GCN: {{buffer|flat}}_load_dword [[REGB:v[0-9]+]]
|
|
|
447 ; GCN: {{buffer|flat}}_load_dword [[REGC:v[0-9]+]]
|
|
|
448
|
|
|
449 ; GCN-FLUSH: v_mac_f32_e32 [[REGC]], [[REGA]], [[REGB]]
|
|
|
450 ; SI-FLUSH: buffer_store_dword [[REGC]]
|
|
|
451 ; VI-FLUSH: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[REGC]]
|
|
|
452
|
|
|
453 ; GCN-DENORM-FASTFMA-CONTRACT: v_fma_f32 [[RESULT:v[0-9]+]], [[REGA]], [[REGB]], [[REGC]]
|
|
|
454
|
|
|
455 ; GCN-DENORM-SLOWFMA-CONTRACT: v_mul_f32_e32 [[TMP:v[0-9]+]], [[REGA]], [[REGB]]
|
|
|
456 ; GCN-DENORM-SLOWFMA-CONTRACT: v_add_f32_e32 [[RESULT:v[0-9]+]], [[REGC]], [[TMP]]
|
|
|
457
|
|
|
458 ; GCN-DENORM-STRICT: v_mul_f32_e32 [[TMP:v[0-9]+]], [[REGA]], [[REGB]]
|
|
|
459 ; GCN-DENORM-STRICT: v_add_f32_e32 [[RESULT:v[0-9]+]], [[REGC]], [[TMP]]
|
|
|
460
|
|
|
461 ; SI-DENORM: buffer_store_dword [[RESULT]]
|
|
|
462 ; VI-DENORM: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
|
|
|
463 define amdgpu_kernel void @neg_neg_mad_f32(float addrspace(1)* noalias nocapture %out, float addrspace(1)* noalias nocapture readonly %ptr) #0 {
|
|
|
464 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0
|
|
|
465 %tid.ext = sext i32 %tid to i64
|
|
|
466 %gep0 = getelementptr float, float addrspace(1)* %ptr, i64 %tid.ext
|
|
|
467 %add1 = add i64 %tid.ext, 1
|
|
|
468 %gep1 = getelementptr float, float addrspace(1)* %ptr, i64 %add1
|
|
|
469 %add2 = add i64 %tid.ext, 2
|
|
|
470 %gep2 = getelementptr float, float addrspace(1)* %ptr, i64 %add2
|
|
|
471 %outgep = getelementptr float, float addrspace(1)* %out, i64 %tid.ext
|
|
|
472 %a = load volatile float, float addrspace(1)* %gep0, align 4
|
|
|
473 %b = load volatile float, float addrspace(1)* %gep1, align 4
|
|
|
474 %c = load volatile float, float addrspace(1)* %gep2, align 4
|
|
|
475 %nega = fsub float -0.000000e+00, %a
|
|
|
476 %negb = fsub float -0.000000e+00, %b
|
|
|
477 %mul = fmul float %nega, %negb
|
|
|
478 %sub = fadd float %mul, %c
|
|
|
479 store float %sub, float addrspace(1)* %outgep, align 4
|
|
|
480 ret void
|
|
|
481 }
|
|
|
482
|
|
|
483 ; GCN-LABEL: {{^}}mad_fabs_sub_f32:
|
|
|
484 ; GCN: {{buffer|flat}}_load_dword [[REGA:v[0-9]+]]
|
|
|
485 ; GCN: {{buffer|flat}}_load_dword [[REGB:v[0-9]+]]
|
|
|
486 ; GCN: {{buffer|flat}}_load_dword [[REGC:v[0-9]+]]
|
|
|
487 ; GCN-FLUSH: v_mad_f32 [[RESULT:v[0-9]+]], [[REGA]], |[[REGB]]|, -[[REGC]]
|
|
|
488
|
|
|
489 ; GCN-DENORM-FASTFMA-CONTRACT: v_fma_f32 [[RESULT:v[0-9]+]], [[REGA]], |[[REGB]]|, -[[REGC]]
|
|
|
490
|
|
|
491 ; GCN-DENORM-SLOWFMA-CONTRACT: v_mul_f32_e64 [[TMP:v[0-9]+]], [[REGA]], |[[REGB]]|
|
|
|
492 ; GCN-DENORM-SLOWFMA-CONTRACT: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[TMP]], [[REGC]]
|
|
|
493
|
|
|
494 ; GCN-DENORM-STRICT: v_mul_f32_e64 [[TMP:v[0-9]+]], [[REGA]], |[[REGB]]|
|
|
|
495 ; GCN-DENORM-STRICT: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[TMP]], [[REGC]]
|
|
|
496
|
|
|
497 ; SI: buffer_store_dword [[RESULT]]
|
|
|
498 ; VI: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
|
|
|
499 define amdgpu_kernel void @mad_fabs_sub_f32(float addrspace(1)* noalias nocapture %out, float addrspace(1)* noalias nocapture readonly %ptr) #0 {
|
|
|
500 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0
|
|
|
501 %tid.ext = sext i32 %tid to i64
|
|
|
502 %gep0 = getelementptr float, float addrspace(1)* %ptr, i64 %tid.ext
|
|
|
503 %add1 = add i64 %tid.ext, 1
|
|
|
504 %gep1 = getelementptr float, float addrspace(1)* %ptr, i64 %add1
|
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505 %add2 = add i64 %tid.ext, 2
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506 %gep2 = getelementptr float, float addrspace(1)* %ptr, i64 %add2
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507 %outgep = getelementptr float, float addrspace(1)* %out, i64 %tid.ext
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508 %a = load volatile float, float addrspace(1)* %gep0, align 4
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509 %b = load volatile float, float addrspace(1)* %gep1, align 4
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510 %c = load volatile float, float addrspace(1)* %gep2, align 4
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511 %b.abs = call float @llvm.fabs.f32(float %b) #0
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512 %mul = fmul float %a, %b.abs
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513 %sub = fsub float %mul, %c
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514 store float %sub, float addrspace(1)* %outgep, align 4
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515 ret void
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516 }
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517
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518 ; GCN-LABEL: {{^}}fsub_c_fadd_a_a_f32:
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519 ; GCN: {{buffer|flat}}_load_dword [[R1:v[0-9]+]],
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520 ; GCN: {{buffer|flat}}_load_dword [[R2:v[0-9]+]],
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521 ; GCN-FLUSH: v_mac_f32_e32 [[R2]], -2.0, [[R1]]
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522 ; SI-FLUSH: buffer_store_dword [[R2]]
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523 ; VI-FLUSH: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[R2]]
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524
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525 ; GCN-DENORM-FASTFMA-CONTRACT: v_fma_f32 [[RESULT:v[0-9]+]], [[R1]], -2.0, [[R2]]
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526
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527 ; GCN-DENORM-SLOWFMA-CONTRACT: v_add_f32_e32 [[TMP:v[0-9]+]], [[R1]], [[R1]]
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528 ; GCN-DENORM-SLOWFMA-CONTRACT: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[R2]], [[TMP]]
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529
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530 ; GCN-DENORM-STRICT: v_add_f32_e32 [[TMP:v[0-9]+]], [[R1]], [[R1]]
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531 ; GCN-DENORM-STRICT: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[R2]], [[TMP]]
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532
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533 ; SI-DENORM: buffer_store_dword [[RESULT]]
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534 ; VI-DENORM: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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535 define amdgpu_kernel void @fsub_c_fadd_a_a_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
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536 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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537 %gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
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538 %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
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539 %gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid
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540
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541 %r1 = load volatile float, float addrspace(1)* %gep.0
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542 %r2 = load volatile float, float addrspace(1)* %gep.1
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543
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544 %add = fadd float %r1, %r1
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545 %r3 = fsub float %r2, %add
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546
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547 store float %r3, float addrspace(1)* %gep.out
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548 ret void
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549 }
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550
|
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551 ; GCN-LABEL: {{^}}fsub_fadd_a_a_c_f32:
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552 ; GCN: {{buffer|flat}}_load_dword [[R1:v[0-9]+]],
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553 ; GCN: {{buffer|flat}}_load_dword [[R2:v[0-9]+]],
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554 ; GCN-FLUSH: v_mad_f32 [[RESULT:v[0-9]+]], [[R1]], 2.0, -[[R2]]
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555
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556 ; GCN-DENORM-FASTFMA-CONTRACT: v_fma_f32 [[RESULT:v[0-9]+]], [[R1]], 2.0, -[[R2]]
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557
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558 ; GCN-DENORM-SLOWFMA-CONTRACT: v_add_f32_e32 [[TMP:v[0-9]+]], [[R1]], [[R1]]
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559 ; GCN-DENORM-SLOWFMA-CONTRACT: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[TMP]], [[R2]]
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560
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561 ; GCN-DENORM-STRICT: v_add_f32_e32 [[TMP:v[0-9]+]], [[R1]], [[R1]]
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562 ; GCN-DENORM-STRICT: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[TMP]], [[R2]]
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563
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564 ; SI: buffer_store_dword [[RESULT]]
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565 ; VI: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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566 define amdgpu_kernel void @fsub_fadd_a_a_c_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
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567 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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568 %gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
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569 %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
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570 %gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid
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571
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572 %r1 = load volatile float, float addrspace(1)* %gep.0
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573 %r2 = load volatile float, float addrspace(1)* %gep.1
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574
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575 %add = fadd float %r1, %r1
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576 %r3 = fsub float %add, %r2
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577
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578 store float %r3, float addrspace(1)* %gep.out
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579 ret void
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580 }
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581
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582 attributes #0 = { nounwind }
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583 attributes #1 = { nounwind readnone }
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