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annotate test/CodeGen/AMDGPU/lds-output-queue.ll @ 128:c347d3398279 default tip

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fix
author mir3636
date Wed, 06 Dec 2017 14:37:17 +0900
parents 803732b1fca8
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
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1 ; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck %s
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2 ;
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3 ; This test checks that the lds input queue will is empty at the end of
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4 ; the ALU clause.
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5
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6 ; CHECK-LABEL: {{^}}lds_input_queue:
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7 ; CHECK: LDS_READ_RET * OQAP
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8 ; CHECK-NOT: ALU clause
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9 ; CHECK: MOV * T{{[0-9]\.[XYZW]}}, OQAP
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10
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11 @local_mem = internal unnamed_addr addrspace(3) global [2 x i32] undef, align 4
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12
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13 define amdgpu_kernel void @lds_input_queue(i32 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %index) {
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14 entry:
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15 %0 = getelementptr inbounds [2 x i32], [2 x i32] addrspace(3)* @local_mem, i32 0, i32 %index
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16 %1 = load i32, i32 addrspace(3)* %0
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17 call void @llvm.r600.group.barrier()
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18
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19 ; This will start a new clause for the vertex fetch
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20 %2 = load i32, i32 addrspace(1)* %in
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21 %3 = add i32 %1, %2
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22 store i32 %3, i32 addrspace(1)* %out
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23 ret void
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24 }
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25
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26 declare void @llvm.r600.group.barrier() nounwind convergent
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27
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28 ; The machine scheduler does not do proper alias analysis and assumes that
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29 ; loads from global values (Note that a global value is different that a
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30 ; value from global memory. A global value is a value that is declared
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31 ; outside of a function, it can reside in any address space) alias with
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32 ; all other loads.
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33 ;
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34 ; This is a problem for scheduling the reads from the local data share (lds).
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35 ; These reads are implemented using two instructions. The first copies the
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36 ; data from lds into the lds output queue, and the second moves the data from
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37 ; the input queue into main memory. These two instructions don't have to be
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38 ; scheduled one after the other, but they do need to be scheduled in the same
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39 ; clause. The aliasing problem mentioned above causes problems when there is a
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40 ; load from global memory which immediately follows a load from a global value that
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41 ; has been declared in the local memory space:
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42 ;
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43 ; %0 = getelementptr inbounds [2 x i32], [2 x i32] addrspace(3)* @local_mem, i32 0, i32 %index
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44 ; %1 = load i32, i32 addrspace(3)* %0
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45 ; %2 = load i32, i32 addrspace(1)* %in
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46 ;
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47 ; The instruction selection phase will generate ISA that looks like this:
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48 ; %OQAP = LDS_READ_RET
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49 ; %vreg0 = MOV %OQAP
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50 ; %vreg1 = VTX_READ_32
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51 ; %vreg2 = ADD_INT %vreg1, %vreg0
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52 ;
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53 ; The bottom scheduler will schedule the two ALU instructions first:
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54 ;
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55 ; UNSCHEDULED:
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56 ; %OQAP = LDS_READ_RET
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57 ; %vreg1 = VTX_READ_32
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58 ;
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59 ; SCHEDULED:
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60 ;
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61 ; vreg0 = MOV %OQAP
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62 ; vreg2 = ADD_INT %vreg1, %vreg2
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63 ;
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64 ; The lack of proper aliasing results in the local memory read (LDS_READ_RET)
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65 ; to consider the global memory read (VTX_READ_32) has a chain dependency, so
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66 ; the global memory read will always be scheduled first. This will give us a
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67 ; final program which looks like this:
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68 ;
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69 ; Alu clause:
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70 ; %OQAP = LDS_READ_RET
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71 ; VTX clause:
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72 ; %vreg1 = VTX_READ_32
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73 ; Alu clause:
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74 ; vreg0 = MOV %OQAP
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75 ; vreg2 = ADD_INT %vreg1, %vreg2
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76 ;
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77 ; This is an illegal program because the OQAP def and use know occur in
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78 ; different ALU clauses.
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79 ;
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80 ; This test checks this scenario and makes sure it doesn't result in an
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81 ; illegal program. For now, we have fixed this issue by merging the
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82 ; LDS_READ_RET and MOV together during instruction selection and then
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83 ; expanding them after scheduling. Once the scheduler has better alias
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84 ; analysis, we should be able to keep these instructions sparate before
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85 ; scheduling.
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86 ;
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87 ; CHECK-LABEL: {{^}}local_global_alias:
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88 ; CHECK: LDS_READ_RET
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89 ; CHECK-NOT: ALU clause
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90 ; CHECK: MOV * T{{[0-9]\.[XYZW]}}, OQAP
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91 define amdgpu_kernel void @local_global_alias(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
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92 entry:
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93 %0 = getelementptr inbounds [2 x i32], [2 x i32] addrspace(3)* @local_mem, i32 0, i32 0
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94 %1 = load i32, i32 addrspace(3)* %0
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95 %2 = load i32, i32 addrspace(1)* %in
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96 %3 = add i32 %2, %1
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97 store i32 %3, i32 addrspace(1)* %out
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98 ret void
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99 }