annotate test/CodeGen/AMDGPU/limit-coalesce.mir @ 128:c347d3398279 default tip

fix
author mir3636
date Wed, 06 Dec 2017 14:37:17 +0900
parents 803732b1fca8
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
121
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1 # RUN: llc -march=amdgcn -run-pass simple-register-coalescing -o - %s | FileCheck %s
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2
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3 # Check that coalescer does not create wider register tuple than in source
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4
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5 # CHECK: - { id: 2, class: vreg_64, preferred-register: '' }
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6 # CHECK: - { id: 3, class: vreg_64, preferred-register: '' }
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7 # CHECK: - { id: 4, class: vreg_64, preferred-register: '' }
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8 # CHECK: - { id: 5, class: vreg_96, preferred-register: '' }
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9 # CHECK: - { id: 6, class: vreg_96, preferred-register: '' }
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10 # CHECK: - { id: 7, class: vreg_128, preferred-register: '' }
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11 # CHECK: - { id: 8, class: vreg_128, preferred-register: '' }
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12 # No more registers shall be defined
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13 # CHECK-NEXT: liveins:
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14 # CHECK: FLAT_STORE_DWORDX2 %vgpr0_vgpr1, %4,
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15 # CHECK: FLAT_STORE_DWORDX3 %vgpr0_vgpr1, %6,
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16
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17 ---
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18 name: main
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19 alignment: 0
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20 exposesReturnsTwice: false
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21 legalized: false
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22 regBankSelected: false
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23 selected: false
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24 tracksRegLiveness: true
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25 registers:
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26 - { id: 1, class: sreg_32_xm0, preferred-register: '%1' }
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27 - { id: 2, class: vreg_64, preferred-register: '%2' }
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28 - { id: 3, class: vreg_64 }
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29 - { id: 4, class: vreg_64 }
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30 - { id: 5, class: vreg_64 }
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31 - { id: 6, class: vreg_96 }
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32 - { id: 7, class: vreg_96 }
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33 - { id: 8, class: vreg_128 }
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34 - { id: 9, class: vreg_128 }
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35 liveins:
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36 - { reg: '%sgpr6', virtual-reg: '%1' }
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37 frameInfo:
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38 isFrameAddressTaken: false
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39 isReturnAddressTaken: false
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40 hasStackMap: false
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41 hasPatchPoint: false
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42 stackSize: 0
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43 offsetAdjustment: 0
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44 maxAlignment: 0
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45 adjustsStack: false
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46 hasCalls: false
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47 maxCallFrameSize: 0
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48 hasOpaqueSPAdjustment: false
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49 hasVAStart: false
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50 hasMustTailInVarArgFunc: false
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51 body: |
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52 bb.0.entry:
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53 liveins: %sgpr0, %vgpr0_vgpr1
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54
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55 %3 = IMPLICIT_DEF
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56 undef %4.sub0 = COPY %sgpr0
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57 %4.sub1 = COPY %3.sub0
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58 undef %5.sub0 = COPY %4.sub1
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59 %5.sub1 = COPY %4.sub0
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60 FLAT_STORE_DWORDX2 %vgpr0_vgpr1, killed %5, 0, 0, 0, implicit %exec, implicit %flat_scr
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61
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62 %6 = IMPLICIT_DEF
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63 undef %7.sub0_sub1 = COPY %6
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64 %7.sub2 = COPY %3.sub0
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65 FLAT_STORE_DWORDX3 %vgpr0_vgpr1, killed %7, 0, 0, 0, implicit %exec, implicit %flat_scr
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66
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67 %8 = IMPLICIT_DEF
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68 undef %9.sub0_sub1_sub2 = COPY %8
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69 %9.sub3 = COPY %3.sub0
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70 FLAT_STORE_DWORDX4 %vgpr0_vgpr1, killed %9, 0, 0, 0, implicit %exec, implicit %flat_scr
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71 ...