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120
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1 ;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=SICI
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2 ;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=VI
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3
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4 ;CHECK-LABEL: {{^}}buffer_load:
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5 ;CHECK: buffer_load_format_xyzw v[0:3], off, s[0:3], 0
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6 ;CHECK: buffer_load_format_xyzw v[4:7], off, s[0:3], 0 glc
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7 ;CHECK: buffer_load_format_xyzw v[8:11], off, s[0:3], 0 slc
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8 ;CHECK: s_waitcnt
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9 define amdgpu_ps {<4 x float>, <4 x float>, <4 x float>} @buffer_load(<4 x i32> inreg) {
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10 main_body:
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11 %data = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 0, i1 0, i1 0)
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12 %data_glc = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 0, i1 1, i1 0)
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13 %data_slc = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 0, i1 0, i1 1)
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14 %r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>} undef, <4 x float> %data, 0
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15 %r1 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r0, <4 x float> %data_glc, 1
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16 %r2 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r1, <4 x float> %data_slc, 2
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17 ret {<4 x float>, <4 x float>, <4 x float>} %r2
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18 }
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19
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20 ;CHECK-LABEL: {{^}}buffer_load_immoffs:
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21 ;CHECK: buffer_load_format_xyzw v[0:3], off, s[0:3], 0 offset:42
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22 ;CHECK: s_waitcnt
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23 define amdgpu_ps <4 x float> @buffer_load_immoffs(<4 x i32> inreg) {
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24 main_body:
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25 %data = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 42, i1 0, i1 0)
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26 ret <4 x float> %data
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27 }
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28
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29 ;CHECK-LABEL: {{^}}buffer_load_immoffs_large:
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121
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30 ;SICI: v_mov_b32_e32 [[VOFS:v[0-9]+]], 0x1038
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120
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31 ;SICI: buffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, [[VOFS]], s[0:3], 0 offen
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32 ;SICI: buffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, s[0:3], 0 offen
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121
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33 ;VI-DAG: buffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, s[0:3], 60 offset:4092
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34 ;VI-DAG: s_movk_i32 [[OFS1:s[0-9]+]], 0x7ffc
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35 ;VI-DAG: buffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, s[0:3], [[OFS1]] offset:4092
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120
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36 ;SICI: buffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, s[0:3], 0 offen
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121
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37 ;VI-DAG: s_mov_b32 [[OFS2:s[0-9]+]], 0x8ffc
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38 ;VI-DAG: buffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, s[0:3], [[OFS2]] offset:4
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120
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39 ;CHECK: s_waitcnt
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40 define amdgpu_ps <4 x float> @buffer_load_immoffs_large(<4 x i32> inreg) {
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41 main_body:
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121
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42 %d.0 = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 4152, i1 0, i1 0)
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43 %d.1 = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 36856, i1 0, i1 0)
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120
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44 %d.2 = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 36864, i1 0, i1 0)
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45 %d.3 = fadd <4 x float> %d.0, %d.1
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46 %data = fadd <4 x float> %d.2, %d.3
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47 ret <4 x float> %data
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48 }
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49
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50 ;CHECK-LABEL: {{^}}buffer_load_immoffs_reuse:
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121
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51 ;VI: s_movk_i32 [[OFS:s[0-9]+]], 0xffc
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52 ;VI: buffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, s[0:3], [[OFS]] offset:68
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120
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53 ;VI-NOT: s_mov
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121
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54 ;VI: buffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, s[0:3], [[OFS]] offset:84
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120
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55 ;VI: s_waitcnt
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56 define amdgpu_ps <4 x float> @buffer_load_immoffs_reuse(<4 x i32> inreg) {
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57 main_body:
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58 %d.0 = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 4160, i1 0, i1 0)
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59 %d.1 = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 4176, i1 0, i1 0)
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60 %data = fadd <4 x float> %d.0, %d.1
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61 ret <4 x float> %data
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62 }
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63
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64 ;CHECK-LABEL: {{^}}buffer_load_idx:
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65 ;CHECK: buffer_load_format_xyzw v[0:3], v0, s[0:3], 0 idxen
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66 ;CHECK: s_waitcnt
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67 define amdgpu_ps <4 x float> @buffer_load_idx(<4 x i32> inreg, i32) {
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68 main_body:
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69 %data = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 %1, i32 0, i1 0, i1 0)
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70 ret <4 x float> %data
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71 }
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72
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73 ;CHECK-LABEL: {{^}}buffer_load_ofs:
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74 ;CHECK: buffer_load_format_xyzw v[0:3], v0, s[0:3], 0 offen
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75 ;CHECK: s_waitcnt
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76 define amdgpu_ps <4 x float> @buffer_load_ofs(<4 x i32> inreg, i32) {
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77 main_body:
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78 %data = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 %1, i1 0, i1 0)
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79 ret <4 x float> %data
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80 }
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81
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82 ;CHECK-LABEL: {{^}}buffer_load_ofs_imm:
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121
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83 ;CHECK: buffer_load_format_xyzw v[0:3], v0, s[0:3], 0 offen offset:60
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120
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84 ;CHECK: s_waitcnt
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85 define amdgpu_ps <4 x float> @buffer_load_ofs_imm(<4 x i32> inreg, i32) {
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86 main_body:
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121
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87 %ofs = add i32 %1, 60
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120
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88 %data = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 %ofs, i1 0, i1 0)
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89 ret <4 x float> %data
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90 }
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91
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92 ;CHECK-LABEL: {{^}}buffer_load_both:
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93 ;CHECK: buffer_load_format_xyzw v[0:3], v[0:1], s[0:3], 0 idxen offen
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94 ;CHECK: s_waitcnt
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95 define amdgpu_ps <4 x float> @buffer_load_both(<4 x i32> inreg, i32, i32) {
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96 main_body:
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97 %data = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 %1, i32 %2, i1 0, i1 0)
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98 ret <4 x float> %data
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99 }
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100
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101 ;CHECK-LABEL: {{^}}buffer_load_both_reversed:
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102 ;CHECK: v_mov_b32_e32 v2, v0
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103 ;CHECK: buffer_load_format_xyzw v[0:3], v[1:2], s[0:3], 0 idxen offen
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104 ;CHECK: s_waitcnt
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105 define amdgpu_ps <4 x float> @buffer_load_both_reversed(<4 x i32> inreg, i32, i32) {
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106 main_body:
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107 %data = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 %2, i32 %1, i1 0, i1 0)
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108 ret <4 x float> %data
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109 }
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110
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111 ;CHECK-LABEL: {{^}}buffer_load_x:
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112 ;CHECK: buffer_load_format_x v0, off, s[0:3], 0
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113 ;CHECK: s_waitcnt
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114 define amdgpu_ps float @buffer_load_x(<4 x i32> inreg %rsrc) {
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115 main_body:
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116 %data = call float @llvm.amdgcn.buffer.load.format.f32(<4 x i32> %rsrc, i32 0, i32 0, i1 0, i1 0)
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117 ret float %data
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118 }
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119
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120 ;CHECK-LABEL: {{^}}buffer_load_xy:
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121 ;CHECK: buffer_load_format_xy v[0:1], off, s[0:3], 0
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122 ;CHECK: s_waitcnt
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123 define amdgpu_ps <2 x float> @buffer_load_xy(<4 x i32> inreg %rsrc) {
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124 main_body:
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125 %data = call <2 x float> @llvm.amdgcn.buffer.load.format.v2f32(<4 x i32> %rsrc, i32 0, i32 0, i1 0, i1 0)
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126 ret <2 x float> %data
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127 }
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128
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129 declare float @llvm.amdgcn.buffer.load.format.f32(<4 x i32>, i32, i32, i1, i1) #0
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130 declare <2 x float> @llvm.amdgcn.buffer.load.format.v2f32(<4 x i32>, i32, i32, i1, i1) #0
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131 declare <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32>, i32, i32, i1, i1) #0
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132
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133 attributes #0 = { nounwind readonly }
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