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annotate test/CodeGen/AMDGPU/llvm.amdgcn.div.fmas.ll @ 128:c347d3398279 default tip

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fix
author mir3636
date Wed, 06 Dec 2017 14:37:17 +0900
parents 803732b1fca8
children
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1 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=GCN -check-prefix=SI %s
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2 ; XUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=GCN -check-prefix=VI %s
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3
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4 ; FIXME: Enable for VI.
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5
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6 declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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7 declare float @llvm.amdgcn.div.fmas.f32(float, float, float, i1) nounwind readnone
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8 declare double @llvm.amdgcn.div.fmas.f64(double, double, double, i1) nounwind readnone
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9
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10 ; GCN-LABEL: {{^}}test_div_fmas_f32:
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11 ; SI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
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12 ; SI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd
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13 ; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
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14 ; VI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c
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15 ; VI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x34
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16 ; VI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x30
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17 ; GCN-DAG: v_mov_b32_e32 [[VC:v[0-9]+]], [[SC]]
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18 ; GCN-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]]
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19 ; GCN-DAG: v_mov_b32_e32 [[VA:v[0-9]+]], [[SA]]
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20 ; GCN: v_div_fmas_f32 [[RESULT:v[0-9]+]], [[VA]], [[VB]], [[VC]]
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21 ; GCN: buffer_store_dword [[RESULT]],
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22 ; GCN: s_endpgm
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23 define amdgpu_kernel void @test_div_fmas_f32(float addrspace(1)* %out, float %a, float %b, float %c, i1 %d) nounwind {
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24 %result = call float @llvm.amdgcn.div.fmas.f32(float %a, float %b, float %c, i1 %d) nounwind readnone
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25 store float %result, float addrspace(1)* %out, align 4
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26 ret void
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27 }
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29 ; GCN-LABEL: {{^}}test_div_fmas_f32_inline_imm_0:
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30 ; SI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd
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31 ; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
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32 ; SI-DAG: v_mov_b32_e32 [[VC:v[0-9]+]], [[SC]]
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33 ; SI-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]]
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34 ; SI: v_div_fmas_f32 [[RESULT:v[0-9]+]], 1.0, [[VB]], [[VC]]
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35 ; SI: buffer_store_dword [[RESULT]],
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36 ; SI: s_endpgm
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37 define amdgpu_kernel void @test_div_fmas_f32_inline_imm_0(float addrspace(1)* %out, float %a, float %b, float %c, i1 %d) nounwind {
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38 %result = call float @llvm.amdgcn.div.fmas.f32(float 1.0, float %b, float %c, i1 %d) nounwind readnone
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39 store float %result, float addrspace(1)* %out, align 4
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40 ret void
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41 }
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42
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43 ; GCN-LABEL: {{^}}test_div_fmas_f32_inline_imm_1:
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44 ; SI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
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45 ; SI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd
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46 ; SI-DAG: v_mov_b32_e32 [[VC:v[0-9]+]], [[SC]]
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47 ; SI-DAG: v_mov_b32_e32 [[VA:v[0-9]+]], [[SA]]
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48 ; SI: v_div_fmas_f32 [[RESULT:v[0-9]+]], [[VA]], 1.0, [[VC]]
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49 ; SI: buffer_store_dword [[RESULT]],
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50 ; SI: s_endpgm
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51 define amdgpu_kernel void @test_div_fmas_f32_inline_imm_1(float addrspace(1)* %out, float %a, float %b, float %c, i1 %d) nounwind {
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52 %result = call float @llvm.amdgcn.div.fmas.f32(float %a, float 1.0, float %c, i1 %d) nounwind readnone
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53 store float %result, float addrspace(1)* %out, align 4
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54 ret void
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55 }
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56
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57 ; GCN-LABEL: {{^}}test_div_fmas_f32_inline_imm_2:
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58 ; SI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
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59 ; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
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60 ; SI-DAG: v_mov_b32_e32 [[VA:v[0-9]+]], [[SA]]
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61 ; SI-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]]
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62 ; SI: v_div_fmas_f32 [[RESULT:v[0-9]+]], [[VA]], [[VB]], 1.0
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63 ; SI: buffer_store_dword [[RESULT]],
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64 ; SI: s_endpgm
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65 define amdgpu_kernel void @test_div_fmas_f32_inline_imm_2(float addrspace(1)* %out, float %a, float %b, float %c, i1 %d) nounwind {
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66 %result = call float @llvm.amdgcn.div.fmas.f32(float %a, float %b, float 1.0, i1 %d) nounwind readnone
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67 store float %result, float addrspace(1)* %out, align 4
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68 ret void
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69 }
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70
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71 ; GCN-LABEL: {{^}}test_div_fmas_f64:
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72 ; GCN: v_div_fmas_f64
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73 define amdgpu_kernel void @test_div_fmas_f64(double addrspace(1)* %out, double %a, double %b, double %c, i1 %d) nounwind {
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74 %result = call double @llvm.amdgcn.div.fmas.f64(double %a, double %b, double %c, i1 %d) nounwind readnone
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75 store double %result, double addrspace(1)* %out, align 8
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76 ret void
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77 }
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78
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79 ; GCN-LABEL: {{^}}test_div_fmas_f32_cond_to_vcc:
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80 ; SI: v_cmp_eq_u32_e64 vcc, s{{[0-9]+}}, 0{{$}}
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81 ; SI: v_div_fmas_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
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82 define amdgpu_kernel void @test_div_fmas_f32_cond_to_vcc(float addrspace(1)* %out, float %a, float %b, float %c, i32 %i) nounwind {
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83 %cmp = icmp eq i32 %i, 0
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84 %result = call float @llvm.amdgcn.div.fmas.f32(float %a, float %b, float %c, i1 %cmp) nounwind readnone
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85 store float %result, float addrspace(1)* %out, align 4
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86 ret void
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87 }
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88
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89 ; GCN-LABEL: {{^}}test_div_fmas_f32_imm_false_cond_to_vcc:
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90 ; SI: s_mov_b64 vcc, 0
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91 ; SI: v_div_fmas_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
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92 define amdgpu_kernel void @test_div_fmas_f32_imm_false_cond_to_vcc(float addrspace(1)* %out, float %a, float %b, float %c) nounwind {
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93 %result = call float @llvm.amdgcn.div.fmas.f32(float %a, float %b, float %c, i1 false) nounwind readnone
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94 store float %result, float addrspace(1)* %out, align 4
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95 ret void
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96 }
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97
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98 ; GCN-LABEL: {{^}}test_div_fmas_f32_imm_true_cond_to_vcc:
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99 ; SI: s_mov_b64 vcc, -1
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100 ; SI: v_div_fmas_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
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101 define amdgpu_kernel void @test_div_fmas_f32_imm_true_cond_to_vcc(float addrspace(1)* %out, float %a, float %b, float %c) nounwind {
100
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102 %result = call float @llvm.amdgcn.div.fmas.f32(float %a, float %b, float %c, i1 true) nounwind readnone
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103 store float %result, float addrspace(1)* %out, align 4
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104 ret void
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105 }
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106
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107 ; GCN-LABEL: {{^}}test_div_fmas_f32_logical_cond_to_vcc:
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108 ; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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109 ; SI-DAG: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}}
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110 ; SI-DAG: buffer_load_dword [[C:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
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111
120
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112 ; SI-DAG: v_cmp_eq_u32_e32 [[CMP0:vcc]], 0, v{{[0-9]+}}
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113 ; SI-DAG: v_cmp_ne_u32_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]], s{{[0-9]+}}, 0{{$}}
100
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114 ; SI: s_and_b64 vcc, [[CMP0]], [[CMP1]]
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115 ; SI: v_div_fmas_f32 {{v[0-9]+}}, [[A]], [[B]], [[C]]
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116 ; SI: s_endpgm
121
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117 define amdgpu_kernel void @test_div_fmas_f32_logical_cond_to_vcc(float addrspace(1)* %out, float addrspace(1)* %in, i32 %d) nounwind {
120
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118 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
100
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119 %gep.a = getelementptr float, float addrspace(1)* %in, i32 %tid
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120 %gep.b = getelementptr float, float addrspace(1)* %gep.a, i32 1
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121 %gep.c = getelementptr float, float addrspace(1)* %gep.a, i32 2
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122 %gep.out = getelementptr float, float addrspace(1)* %out, i32 2
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123
120
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124 %a = load volatile float, float addrspace(1)* %gep.a
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125 %b = load volatile float, float addrspace(1)* %gep.b
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126 %c = load volatile float, float addrspace(1)* %gep.c
100
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127
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128 %cmp0 = icmp eq i32 %tid, 0
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129 %cmp1 = icmp ne i32 %d, 0
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130 %and = and i1 %cmp0, %cmp1
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131
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132 %result = call float @llvm.amdgcn.div.fmas.f32(float %a, float %b, float %c, i1 %and) nounwind readnone
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133 store float %result, float addrspace(1)* %gep.out, align 4
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134 ret void
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135 }
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136
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137 ; GCN-LABEL: {{^}}test_div_fmas_f32_i1_phi_vcc:
120
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138 ; SI: v_cmp_eq_u32_e32 vcc, 0, v{{[0-9]+}}
100
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139 ; SI: s_and_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], vcc
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140
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141 ; SI: buffer_load_dword [[LOAD:v[0-9]+]]
120
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142 ; SI: v_cmp_ne_u32_e32 vcc, 0, [[LOAD]]
100
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143 ; SI: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc
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144
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145
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146 ; SI: BB9_2:
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147 ; SI: s_or_b64 exec, exec, [[SAVE]]
120
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148 ; SI: v_cmp_ne_u32_e32 vcc, 0, v{{[0-9]+}}
100
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149 ; SI: v_div_fmas_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
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150 ; SI: buffer_store_dword
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151 ; SI: s_endpgm
121
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152 define amdgpu_kernel void @test_div_fmas_f32_i1_phi_vcc(float addrspace(1)* %out, float addrspace(1)* %in, i32 addrspace(1)* %dummy) nounwind {
100
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153 entry:
120
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154 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
100
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155 %gep.out = getelementptr float, float addrspace(1)* %out, i32 2
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156 %gep.a = getelementptr float, float addrspace(1)* %in, i32 %tid
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157 %gep.b = getelementptr float, float addrspace(1)* %gep.a, i32 1
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158 %gep.c = getelementptr float, float addrspace(1)* %gep.a, i32 2
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159
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160 %a = load float, float addrspace(1)* %gep.a
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161 %b = load float, float addrspace(1)* %gep.b
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162 %c = load float, float addrspace(1)* %gep.c
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163
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164 %cmp0 = icmp eq i32 %tid, 0
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165 br i1 %cmp0, label %bb, label %exit
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166
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167 bb:
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168 %val = load i32, i32 addrspace(1)* %dummy
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169 %cmp1 = icmp ne i32 %val, 0
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170 br label %exit
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171
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172 exit:
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173 %cond = phi i1 [false, %entry], [%cmp1, %bb]
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174 %result = call float @llvm.amdgcn.div.fmas.f32(float %a, float %b, float %c, i1 %cond) nounwind readnone
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175 store float %result, float addrspace(1)* %gep.out, align 4
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176 ret void
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177 }