annotate test/CodeGen/AMDGPU/llvm.amdgcn.frexp.exp.ll @ 128:c347d3398279 default tip

fix
author mir3636
date Wed, 06 Dec 2017 14:37:17 +0900
parents 803732b1fca8
children
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1 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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2 ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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3
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4 declare float @llvm.fabs.f32(float) #0
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5 declare double @llvm.fabs.f64(double) #0
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6 declare i32 @llvm.amdgcn.frexp.exp.i32.f32(float) #0
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7 declare i32 @llvm.amdgcn.frexp.exp.i32.f64(double) #0
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8
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9 ; GCN-LABEL: {{^}}s_test_frexp_exp_f32:
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10 ; GCN: v_frexp_exp_i32_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}
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11 define amdgpu_kernel void @s_test_frexp_exp_f32(i32 addrspace(1)* %out, float %src) #1 {
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12 %frexp.exp = call i32 @llvm.amdgcn.frexp.exp.i32.f32(float %src)
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13 store i32 %frexp.exp, i32 addrspace(1)* %out
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14 ret void
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15 }
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16
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17 ; GCN-LABEL: {{^}}s_test_fabs_frexp_exp_f32:
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18 ; GCN: v_frexp_exp_i32_f32_e64 {{v[0-9]+}}, |{{s[0-9]+}}|
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19 define amdgpu_kernel void @s_test_fabs_frexp_exp_f32(i32 addrspace(1)* %out, float %src) #1 {
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20 %fabs.src = call float @llvm.fabs.f32(float %src)
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21 %frexp.exp = call i32 @llvm.amdgcn.frexp.exp.i32.f32(float %fabs.src)
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22 store i32 %frexp.exp, i32 addrspace(1)* %out
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23 ret void
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24 }
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25
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26 ; GCN-LABEL: {{^}}s_test_fneg_fabs_frexp_exp_f32:
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27 ; GCN: v_frexp_exp_i32_f32_e64 {{v[0-9]+}}, -|{{s[0-9]+}}|
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28 define amdgpu_kernel void @s_test_fneg_fabs_frexp_exp_f32(i32 addrspace(1)* %out, float %src) #1 {
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29 %fabs.src = call float @llvm.fabs.f32(float %src)
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30 %fneg.fabs.src = fsub float -0.0, %fabs.src
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31 %frexp.exp = call i32 @llvm.amdgcn.frexp.exp.i32.f32(float %fneg.fabs.src)
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32 store i32 %frexp.exp, i32 addrspace(1)* %out
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33 ret void
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34 }
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35
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36 ; GCN-LABEL: {{^}}s_test_frexp_exp_f64:
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37 ; GCN: v_frexp_exp_i32_f64_e32 {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}
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38 define amdgpu_kernel void @s_test_frexp_exp_f64(i32 addrspace(1)* %out, double %src) #1 {
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39 %frexp.exp = call i32 @llvm.amdgcn.frexp.exp.i32.f64(double %src)
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40 store i32 %frexp.exp, i32 addrspace(1)* %out
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41 ret void
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42 }
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43
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44 ; GCN-LABEL: {{^}}s_test_fabs_frexp_exp_f64:
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45 ; GCN: v_frexp_exp_i32_f64_e64 {{v[0-9]+}}, |{{s\[[0-9]+:[0-9]+\]}}|
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46 define amdgpu_kernel void @s_test_fabs_frexp_exp_f64(i32 addrspace(1)* %out, double %src) #1 {
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47 %fabs.src = call double @llvm.fabs.f64(double %src)
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48 %frexp.exp = call i32 @llvm.amdgcn.frexp.exp.i32.f64(double %fabs.src)
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49 store i32 %frexp.exp, i32 addrspace(1)* %out
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50 ret void
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51 }
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52
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53 ; GCN-LABEL: {{^}}s_test_fneg_fabs_frexp_exp_f64:
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54 ; GCN: v_frexp_exp_i32_f64_e64 {{v[0-9]+}}, -|{{s\[[0-9]+:[0-9]+\]}}|
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55 define amdgpu_kernel void @s_test_fneg_fabs_frexp_exp_f64(i32 addrspace(1)* %out, double %src) #1 {
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56 %fabs.src = call double @llvm.fabs.f64(double %src)
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57 %fneg.fabs.src = fsub double -0.0, %fabs.src
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58 %frexp.exp = call i32 @llvm.amdgcn.frexp.exp.i32.f64(double %fneg.fabs.src)
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59 store i32 %frexp.exp, i32 addrspace(1)* %out
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60 ret void
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61 }
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62
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63 attributes #0 = { nounwind readnone }
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64 attributes #1 = { nounwind }