|
120
|
1 ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,HSA,ALL,HSA-NOENV %s
|
|
|
2 ; RUN: llc -mtriple=amdgcn--amdhsa-opencl -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,HSA,ALL,HSA-OPENCL %s
|
|
|
3 ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,OS-MESA3D,MESA,ALL %s
|
|
|
4 ; RUN: llc -mtriple=amdgcn-mesa-unknown -verify-machineinstrs < %s | FileCheck -check-prefixes=OS-UNKNOWN,MESA,ALL %s
|
|
121
|
5 ; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,HSA,ALL,HSA-NOENV %s
|
|
|
6 ; RUN: llc -mtriple=amdgcn--amdhsa-amdgizcl -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,HSA,ALL,HSA-OPENCL %s
|
|
120
|
7
|
|
|
8 ; ALL-LABEL: {{^}}test:
|
|
|
9 ; CO-V2: enable_sgpr_kernarg_segment_ptr = 1
|
|
|
10 ; CO-V2: s_load_dword s{{[0-9]+}}, s[4:5], 0xa
|
|
|
11
|
|
|
12 ; OS-UNKNOWN: s_load_dword s{{[0-9]+}}, s[0:1], 0xa
|
|
121
|
13 define amdgpu_kernel void @test(i32 addrspace(1)* %out) #1 {
|
|
120
|
14 %kernarg.segment.ptr = call noalias i8 addrspace(2)* @llvm.amdgcn.kernarg.segment.ptr()
|
|
|
15 %header.ptr = bitcast i8 addrspace(2)* %kernarg.segment.ptr to i32 addrspace(2)*
|
|
|
16 %gep = getelementptr i32, i32 addrspace(2)* %header.ptr, i64 10
|
|
|
17 %value = load i32, i32 addrspace(2)* %gep
|
|
|
18 store i32 %value, i32 addrspace(1)* %out
|
|
|
19 ret void
|
|
|
20 }
|
|
|
21
|
|
|
22 ; ALL-LABEL: {{^}}test_implicit:
|
|
|
23 ; 10 + 9 (36 prepended implicit bytes) + 2(out pointer) = 21 = 0x15
|
|
|
24 ; OS-UNKNOWN: s_load_dword s{{[0-9]+}}, s[0:1], 0x15
|
|
121
|
25 define amdgpu_kernel void @test_implicit(i32 addrspace(1)* %out) #1 {
|
|
120
|
26 %implicitarg.ptr = call noalias i8 addrspace(2)* @llvm.amdgcn.implicitarg.ptr()
|
|
|
27 %header.ptr = bitcast i8 addrspace(2)* %implicitarg.ptr to i32 addrspace(2)*
|
|
|
28 %gep = getelementptr i32, i32 addrspace(2)* %header.ptr, i64 10
|
|
|
29 %value = load i32, i32 addrspace(2)* %gep
|
|
|
30 store i32 %value, i32 addrspace(1)* %out
|
|
|
31 ret void
|
|
|
32 }
|
|
|
33
|
|
|
34 ; ALL-LABEL: {{^}}test_implicit_alignment
|
|
|
35 ; HSA-NOENV: kernarg_segment_byte_size = 10
|
|
|
36 ; HSA-OPENCL: kernarg_segment_byte_size = 48
|
|
|
37 ; OS-MESA3D: kernarg_segment_byte_size = 28
|
|
|
38 ; OS-UNKNOWN: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xc
|
|
|
39 ; HSA: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x4
|
|
|
40 ; OS-MESA3D: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x3
|
|
|
41 ; ALL: v_mov_b32_e32 [[V_VAL:v[0-9]+]], [[VAL]]
|
|
|
42 ; MESA: buffer_store_dword [[V_VAL]]
|
|
|
43 ; HSA: flat_store_dword v[{{[0-9]+:[0-9]+}}], [[V_VAL]]
|
|
121
|
44 define amdgpu_kernel void @test_implicit_alignment(i32 addrspace(1)* %out, <2 x i8> %in) #1 {
|
|
120
|
45 %implicitarg.ptr = call noalias i8 addrspace(2)* @llvm.amdgcn.implicitarg.ptr()
|
|
|
46 %arg.ptr = bitcast i8 addrspace(2)* %implicitarg.ptr to i32 addrspace(2)*
|
|
|
47 %val = load i32, i32 addrspace(2)* %arg.ptr
|
|
|
48 store i32 %val, i32 addrspace(1)* %out
|
|
|
49 ret void
|
|
|
50 }
|
|
|
51
|
|
121
|
52 ; ALL-LABEL: {{^}}test_no_kernargs:
|
|
|
53 ; HSA: enable_sgpr_kernarg_segment_ptr = 1
|
|
|
54 ; HSA: s_load_dword s{{[0-9]+}}, s[4:5]
|
|
|
55 define amdgpu_kernel void @test_no_kernargs() #1 {
|
|
|
56 %kernarg.segment.ptr = call noalias i8 addrspace(2)* @llvm.amdgcn.kernarg.segment.ptr()
|
|
|
57 %header.ptr = bitcast i8 addrspace(2)* %kernarg.segment.ptr to i32 addrspace(2)*
|
|
|
58 %gep = getelementptr i32, i32 addrspace(2)* %header.ptr, i64 10
|
|
|
59 %value = load i32, i32 addrspace(2)* %gep
|
|
|
60 store volatile i32 %value, i32 addrspace(1)* undef
|
|
|
61 ret void
|
|
|
62 }
|
|
|
63
|
|
120
|
64 declare i8 addrspace(2)* @llvm.amdgcn.kernarg.segment.ptr() #0
|
|
|
65 declare i8 addrspace(2)* @llvm.amdgcn.implicitarg.ptr() #0
|
|
|
66
|
|
|
67 attributes #0 = { nounwind readnone }
|
|
|
68 attributes #1 = { nounwind }
|
