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1 ; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=SI %s
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2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=SI %s
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3
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4 ; SI-LABEL: {{^}}gs_const:
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5 ; SI-NOT: v_cmpx
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6 ; SI: s_mov_b64 exec, 0
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7 define amdgpu_gs void @gs_const() {
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8 %tmp = icmp ule i32 0, 3
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9 %tmp1 = select i1 %tmp, float 1.000000e+00, float -1.000000e+00
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10 %c1 = fcmp oge float %tmp1, 0.0
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11 call void @llvm.amdgcn.kill(i1 %c1)
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12 %tmp2 = icmp ule i32 3, 0
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13 %tmp3 = select i1 %tmp2, float 1.000000e+00, float -1.000000e+00
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14 %c2 = fcmp oge float %tmp3, 0.0
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15 call void @llvm.amdgcn.kill(i1 %c2)
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16 ret void
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17 }
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18
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19 ; SI-LABEL: {{^}}vcc_implicit_def:
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20 ; SI-NOT: v_cmp_gt_f32_e32 vcc,
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21 ; SI: v_cmp_gt_f32_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], 0, v{{[0-9]+}}
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22 ; SI: v_cmpx_le_f32_e32 vcc, 0, v{{[0-9]+}}
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23 ; SI: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1.0, [[CMP]]
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24 define amdgpu_ps void @vcc_implicit_def(float %arg13, float %arg14) {
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25 %tmp0 = fcmp olt float %arg13, 0.000000e+00
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26 %c1 = fcmp oge float %arg14, 0.0
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27 call void @llvm.amdgcn.kill(i1 %c1)
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28 %tmp1 = select i1 %tmp0, float 1.000000e+00, float 0.000000e+00
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29 call void @llvm.amdgcn.exp.f32(i32 1, i32 15, float %tmp1, float %tmp1, float %tmp1, float %tmp1, i1 true, i1 true) #0
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30 ret void
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31 }
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32
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33 ; SI-LABEL: {{^}}true:
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34 ; SI-NEXT: BB#
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35 ; SI-NEXT: BB#
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36 ; SI-NEXT: s_endpgm
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37 define amdgpu_gs void @true() {
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38 call void @llvm.amdgcn.kill(i1 true)
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39 ret void
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40 }
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41
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42 ; SI-LABEL: {{^}}false:
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43 ; SI-NOT: v_cmpx
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44 ; SI: s_mov_b64 exec, 0
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45 define amdgpu_gs void @false() {
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46 call void @llvm.amdgcn.kill(i1 false)
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47 ret void
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48 }
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49
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50 ; SI-LABEL: {{^}}and:
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51 ; SI: v_cmp_lt_i32
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52 ; SI: v_cmp_lt_i32
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53 ; SI: s_or_b64 s[0:1]
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54 ; SI: s_and_b64 exec, exec, s[0:1]
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55 define amdgpu_gs void @and(i32 %a, i32 %b, i32 %c, i32 %d) {
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56 %c1 = icmp slt i32 %a, %b
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57 %c2 = icmp slt i32 %c, %d
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58 %x = or i1 %c1, %c2
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59 call void @llvm.amdgcn.kill(i1 %x)
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60 ret void
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61 }
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62
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63 ; SI-LABEL: {{^}}andn2:
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64 ; SI: v_cmp_lt_i32
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65 ; SI: v_cmp_lt_i32
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66 ; SI: s_xor_b64 s[0:1]
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67 ; SI: s_andn2_b64 exec, exec, s[0:1]
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68 define amdgpu_gs void @andn2(i32 %a, i32 %b, i32 %c, i32 %d) {
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69 %c1 = icmp slt i32 %a, %b
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70 %c2 = icmp slt i32 %c, %d
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71 %x = xor i1 %c1, %c2
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72 %y = xor i1 %x, 1
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73 call void @llvm.amdgcn.kill(i1 %y)
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74 ret void
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75 }
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76
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77 ; SI-LABEL: {{^}}oeq:
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78 ; SI: v_cmpx_eq_f32
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79 ; SI-NOT: s_and
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80 define amdgpu_gs void @oeq(float %a) {
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81 %c1 = fcmp oeq float %a, 0.0
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82 call void @llvm.amdgcn.kill(i1 %c1)
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83 ret void
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84 }
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85
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86 ; SI-LABEL: {{^}}ogt:
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87 ; SI: v_cmpx_lt_f32
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88 ; SI-NOT: s_and
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89 define amdgpu_gs void @ogt(float %a) {
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90 %c1 = fcmp ogt float %a, 0.0
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91 call void @llvm.amdgcn.kill(i1 %c1)
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92 ret void
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93 }
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94
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95 ; SI-LABEL: {{^}}oge:
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96 ; SI: v_cmpx_le_f32
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97 ; SI-NOT: s_and
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98 define amdgpu_gs void @oge(float %a) {
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99 %c1 = fcmp oge float %a, 0.0
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100 call void @llvm.amdgcn.kill(i1 %c1)
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101 ret void
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102 }
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103
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104 ; SI-LABEL: {{^}}olt:
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105 ; SI: v_cmpx_gt_f32
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106 ; SI-NOT: s_and
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107 define amdgpu_gs void @olt(float %a) {
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108 %c1 = fcmp olt float %a, 0.0
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109 call void @llvm.amdgcn.kill(i1 %c1)
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110 ret void
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111 }
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112
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113 ; SI-LABEL: {{^}}ole:
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114 ; SI: v_cmpx_ge_f32
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115 ; SI-NOT: s_and
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116 define amdgpu_gs void @ole(float %a) {
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117 %c1 = fcmp ole float %a, 0.0
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118 call void @llvm.amdgcn.kill(i1 %c1)
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119 ret void
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120 }
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121
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122 ; SI-LABEL: {{^}}one:
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123 ; SI: v_cmpx_lg_f32
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124 ; SI-NOT: s_and
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125 define amdgpu_gs void @one(float %a) {
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126 %c1 = fcmp one float %a, 0.0
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127 call void @llvm.amdgcn.kill(i1 %c1)
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128 ret void
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129 }
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130
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131 ; SI-LABEL: {{^}}ord:
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132 ; FIXME: This is absolutely unimportant, but we could use the cmpx variant here.
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133 ; SI: v_cmp_o_f32
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134 define amdgpu_gs void @ord(float %a) {
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135 %c1 = fcmp ord float %a, 0.0
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136 call void @llvm.amdgcn.kill(i1 %c1)
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137 ret void
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138 }
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139
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140 ; SI-LABEL: {{^}}uno:
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141 ; FIXME: This is absolutely unimportant, but we could use the cmpx variant here.
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142 ; SI: v_cmp_u_f32
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143 define amdgpu_gs void @uno(float %a) {
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144 %c1 = fcmp uno float %a, 0.0
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145 call void @llvm.amdgcn.kill(i1 %c1)
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146 ret void
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147 }
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148
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149 ; SI-LABEL: {{^}}ueq:
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150 ; SI: v_cmpx_nlg_f32
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151 ; SI-NOT: s_and
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152 define amdgpu_gs void @ueq(float %a) {
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153 %c1 = fcmp ueq float %a, 0.0
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154 call void @llvm.amdgcn.kill(i1 %c1)
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155 ret void
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156 }
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157
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158 ; SI-LABEL: {{^}}ugt:
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159 ; SI: v_cmpx_nge_f32
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160 ; SI-NOT: s_and
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161 define amdgpu_gs void @ugt(float %a) {
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162 %c1 = fcmp ugt float %a, 0.0
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163 call void @llvm.amdgcn.kill(i1 %c1)
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164 ret void
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165 }
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166
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167 ; SI-LABEL: {{^}}uge:
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168 ; SI: v_cmpx_ngt_f32_e32 vcc, -1.0
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169 ; SI-NOT: s_and
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170 define amdgpu_gs void @uge(float %a) {
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171 %c1 = fcmp uge float %a, -1.0
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172 call void @llvm.amdgcn.kill(i1 %c1)
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173 ret void
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174 }
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175
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176 ; SI-LABEL: {{^}}ult:
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177 ; SI: v_cmpx_nle_f32_e32 vcc, -2.0
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178 ; SI-NOT: s_and
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179 define amdgpu_gs void @ult(float %a) {
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180 %c1 = fcmp ult float %a, -2.0
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181 call void @llvm.amdgcn.kill(i1 %c1)
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182 ret void
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183 }
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184
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185 ; SI-LABEL: {{^}}ule:
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186 ; SI: v_cmpx_nlt_f32_e32 vcc, 2.0
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187 ; SI-NOT: s_and
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188 define amdgpu_gs void @ule(float %a) {
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189 %c1 = fcmp ule float %a, 2.0
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190 call void @llvm.amdgcn.kill(i1 %c1)
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191 ret void
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192 }
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193
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194 ; SI-LABEL: {{^}}une:
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195 ; SI: v_cmpx_neq_f32_e32 vcc, 0
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196 ; SI-NOT: s_and
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197 define amdgpu_gs void @une(float %a) {
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198 %c1 = fcmp une float %a, 0.0
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199 call void @llvm.amdgcn.kill(i1 %c1)
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200 ret void
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201 }
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202
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203 ; SI-LABEL: {{^}}neg_olt:
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204 ; SI: v_cmpx_ngt_f32_e32 vcc, 1.0
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205 ; SI-NOT: s_and
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206 define amdgpu_gs void @neg_olt(float %a) {
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207 %c1 = fcmp olt float %a, 1.0
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208 %c2 = xor i1 %c1, 1
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209 call void @llvm.amdgcn.kill(i1 %c2)
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210 ret void
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211 }
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212
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213 ; SI-LABEL: {{^}}fcmp_x2:
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214 ; FIXME: LLVM should be able to combine these fcmp opcodes.
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215 ; SI: v_cmp_gt_f32
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216 ; SI: v_cndmask_b32
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217 ; SI: v_cmpx_le_f32
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218 define amdgpu_ps void @fcmp_x2(float %a) #0 {
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219 %ogt = fcmp nsz ogt float %a, 2.500000e-01
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220 %k = select i1 %ogt, float -1.000000e+00, float 0.000000e+00
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221 %c = fcmp nsz oge float %k, 0.000000e+00
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222 call void @llvm.amdgcn.kill(i1 %c) #1
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223 ret void
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224 }
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225
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226 ; SI-LABEL: {{^}}wqm:
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227 ; SI: v_cmp_neq_f32_e32 vcc, 0
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228 ; SI: s_wqm_b64 s[0:1], vcc
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229 ; SI: s_and_b64 exec, exec, s[0:1]
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230 define amdgpu_ps void @wqm(float %a) {
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231 %c1 = fcmp une float %a, 0.0
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232 %c2 = call i1 @llvm.amdgcn.wqm.vote(i1 %c1)
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233 call void @llvm.amdgcn.kill(i1 %c2)
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234 ret void
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235 }
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236
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237 declare void @llvm.amdgcn.kill(i1) #0
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238 declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0
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239 declare i1 @llvm.amdgcn.wqm.vote(i1)
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240
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241 attributes #0 = { nounwind }
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