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120
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1 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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2 ; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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3
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4 declare <4 x i32> @llvm.amdgcn.mqsad.u32.u8(i64, i32, <4 x i32>) #0
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5
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121
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6 ; GCN-LABEL: {{^}}v_mqsad_u32_u8_inline_integer_immediate:
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7 ; GCN-DAG: v_mov_b32_e32 v0, v2
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8 ; GCN-DAG: v_mov_b32_e32 v1, v3
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9 ; GCN: v_mqsad_u32_u8 v[2:5], v[0:1], v6, v[{{[0-9]+:[0-9]+}}]
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10 define amdgpu_kernel void @v_mqsad_u32_u8_inline_integer_immediate(<4 x i32> addrspace(1)* %out, i64 %src, i32 %a) {
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11 %tmp = call i64 asm "v_lsrlrev_b64 $0, $1, 1", "={v[2:3]},v"(i64 %src) #0
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12 %tmp1 = call i32 asm "v_mov_b32 $0, $1", "={v4},v"(i32 %a) #0
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13 %tmp2 = call <4 x i32> @llvm.amdgcn.mqsad.u32.u8(i64 %tmp, i32 %tmp1, <4 x i32> <i32 10, i32 20, i32 30, i32 40>) #0
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14 %tmp3 = call <4 x i32> asm ";; force constraint", "=v,{v[2:5]}"(<4 x i32> %tmp2) #0
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15 store <4 x i32> %tmp3, <4 x i32> addrspace(1)* %out, align 4
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120
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16 ret void
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17 }
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18
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19 ; GCN-LABEL: {{^}}v_mqsad_u32_u8_non_immediate:
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121
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20 ; GCN-DAG: v_mov_b32_e32 v0, v2
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21 ; GCN-DAG: v_mov_b32_e32 v1, v3
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22 ; GCN: v_mqsad_u32_u8 v[2:5], v[0:1], v6, v[{{[0-9]+:[0-9]+}}]
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23 define amdgpu_kernel void @v_mqsad_u32_u8_non_immediate(<4 x i32> addrspace(1)* %out, i64 %src, i32 %a, <4 x i32> %b) {
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24 %tmp = call i64 asm "v_lsrlrev_b64 $0, $1, 1", "={v[2:3]},v"(i64 %src) #0
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25 %tmp1 = call i32 asm "v_mov_b32 $0, $1", "={v4},v"(i32 %a) #0
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26 %tmp2 = call <4 x i32> @llvm.amdgcn.mqsad.u32.u8(i64 %tmp, i32 %tmp1, <4 x i32> %b) #0
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27 %tmp3 = call <4 x i32> asm ";; force constraint", "=v,{v[2:5]}"(<4 x i32> %tmp2) #0
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28 store <4 x i32> %tmp3, <4 x i32> addrspace(1)* %out, align 4
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120
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29 ret void
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30 }
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31
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32 ; GCN-LABEL: {{^}}v_mqsad_u32_u8_inline_fp_immediate:
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121
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33 ; GCN-DAG: v_mov_b32_e32 v0, v2
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34 ; GCN-DAG: v_mov_b32_e32 v1, v3
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35 ; GCN: v_mqsad_u32_u8 v[2:5], v[0:1], v6, v[{{[0-9]+:[0-9]+}}]
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36 define amdgpu_kernel void @v_mqsad_u32_u8_inline_fp_immediate(<4 x i32> addrspace(1)* %out, i64 %src, i32 %a) {
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37 %tmp = call i64 asm "v_lsrlrev_b64 $0, $1, 1", "={v[2:3]},v"(i64 %src) #0
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38 %tmp1 = call i32 asm "v_mov_b32 $0, $1", "={v4},v"(i32 %a) #0
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39 %tmp2 = call <4 x i32> @llvm.amdgcn.mqsad.u32.u8(i64 %tmp, i32 %tmp1, <4 x i32> <i32 1065353216, i32 0, i32 0, i32 0>) #0
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40 %tmp3 = call <4 x i32> asm ";; force constraint", "=v,{v[2:5]}"(<4 x i32> %tmp2) #0
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41 store <4 x i32> %tmp3, <4 x i32> addrspace(1)* %out, align 4
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120
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42 ret void
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43 }
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44
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45 ; GCN-LABEL: {{^}}v_mqsad_u32_u8_use_sgpr_vgpr:
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121
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46 ; GCN-DAG: v_mov_b32_e32 v0, v2
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47 ; GCN-DAG: v_mov_b32_e32 v1, v3
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48 ; GCN: v_mqsad_u32_u8 v[2:5], v[0:1], v6, v[{{[0-9]+:[0-9]+}}]
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49 define amdgpu_kernel void @v_mqsad_u32_u8_use_sgpr_vgpr(<4 x i32> addrspace(1)* %out, i64 %src, i32 %a, <4 x i32> addrspace(1)* %input) {
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120
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50 %in = load <4 x i32>, <4 x i32> addrspace(1) * %input
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121
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51 %tmp = call i64 asm "v_lsrlrev_b64 $0, $1, 1", "={v[2:3]},v"(i64 %src) #0
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52 %tmp1 = call i32 asm "v_mov_b32 $0, $1", "={v4},v"(i32 %a) #0
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53 %tmp2 = call <4 x i32> @llvm.amdgcn.mqsad.u32.u8(i64 %tmp, i32 %tmp1, <4 x i32> %in) #0
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54 %tmp3 = call <4 x i32> asm ";; force constraint", "=v,{v[2:5]}"(<4 x i32> %tmp2) #0
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55 store <4 x i32> %tmp3, <4 x i32> addrspace(1)* %out, align 4
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120
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56 ret void
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57 }
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58
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59 attributes #0 = { nounwind readnone }
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