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annotate test/CodeGen/AMDGPU/llvm.amdgcn.rcp.ll @ 128:c347d3398279 default tip

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fix
author mir3636
date Wed, 06 Dec 2017 14:37:17 +0900
parents 803732b1fca8
children
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rev   line source
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1 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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2
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3 declare float @llvm.amdgcn.rcp.f32(float) #0
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4 declare double @llvm.amdgcn.rcp.f64(double) #0
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5
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6 declare double @llvm.sqrt.f64(double) #0
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7 declare float @llvm.sqrt.f32(float) #0
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8
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9 ; FUNC-LABEL: {{^}}rcp_undef_f32:
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10 ; SI-NOT: v_rcp_f32
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11 define amdgpu_kernel void @rcp_undef_f32(float addrspace(1)* %out) #1 {
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12 %rcp = call float @llvm.amdgcn.rcp.f32(float undef)
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13 store float %rcp, float addrspace(1)* %out, align 4
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14 ret void
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15 }
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16
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17 ; FUNC-LABEL: {{^}}rcp_2_f32:
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18 ; SI-NOT: v_rcp_f32
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19 ; SI: v_mov_b32_e32 v{{[0-9]+}}, 0.5
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20 define amdgpu_kernel void @rcp_2_f32(float addrspace(1)* %out) #1 {
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21 %rcp = call float @llvm.amdgcn.rcp.f32(float 2.0)
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22 store float %rcp, float addrspace(1)* %out, align 4
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23 ret void
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24 }
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25
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26 ; FUNC-LABEL: {{^}}rcp_10_f32:
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27 ; SI-NOT: v_rcp_f32
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28 ; SI: v_mov_b32_e32 v{{[0-9]+}}, 0x3dcccccd
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29 define amdgpu_kernel void @rcp_10_f32(float addrspace(1)* %out) #1 {
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30 %rcp = call float @llvm.amdgcn.rcp.f32(float 10.0)
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31 store float %rcp, float addrspace(1)* %out, align 4
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32 ret void
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33 }
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34
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35 ; FUNC-LABEL: {{^}}safe_no_fp32_denormals_rcp_f32:
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36 ; SI: v_rcp_f32_e32 [[RESULT:v[0-9]+]], s{{[0-9]+}}
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37 ; SI-NOT: [[RESULT]]
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38 ; SI: buffer_store_dword [[RESULT]]
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39 define amdgpu_kernel void @safe_no_fp32_denormals_rcp_f32(float addrspace(1)* %out, float %src) #1 {
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40 %rcp = fdiv float 1.0, %src
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41 store float %rcp, float addrspace(1)* %out, align 4
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42 ret void
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43 }
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44
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45 ; FUNC-LABEL: {{^}}safe_f32_denormals_rcp_pat_f32:
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46 ; SI: v_rcp_f32_e32 [[RESULT:v[0-9]+]], s{{[0-9]+}}
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47 ; SI-NOT: [[RESULT]]
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48 ; SI: buffer_store_dword [[RESULT]]
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49 define amdgpu_kernel void @safe_f32_denormals_rcp_pat_f32(float addrspace(1)* %out, float %src) #4 {
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50 %rcp = fdiv float 1.0, %src
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51 store float %rcp, float addrspace(1)* %out, align 4
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52 ret void
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53 }
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54
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55 ; FUNC-LABEL: {{^}}unsafe_f32_denormals_rcp_pat_f32:
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56 ; SI: v_div_scale_f32
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57 define amdgpu_kernel void @unsafe_f32_denormals_rcp_pat_f32(float addrspace(1)* %out, float %src) #3 {
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58 %rcp = fdiv float 1.0, %src
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59 store float %rcp, float addrspace(1)* %out, align 4
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60 ret void
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61 }
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62
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63 ; FUNC-LABEL: {{^}}safe_rsq_rcp_pat_f32:
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64 ; SI: v_sqrt_f32_e32
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65 ; SI: v_rcp_f32_e32
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66 define amdgpu_kernel void @safe_rsq_rcp_pat_f32(float addrspace(1)* %out, float %src) #1 {
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67 %sqrt = call float @llvm.sqrt.f32(float %src)
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68 %rcp = call float @llvm.amdgcn.rcp.f32(float %sqrt)
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69 store float %rcp, float addrspace(1)* %out, align 4
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70 ret void
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71 }
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72
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73 ; FUNC-LABEL: {{^}}unsafe_rsq_rcp_pat_f32:
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74 ; SI: v_rsq_f32_e32
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75 define amdgpu_kernel void @unsafe_rsq_rcp_pat_f32(float addrspace(1)* %out, float %src) #2 {
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76 %sqrt = call float @llvm.sqrt.f32(float %src)
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77 %rcp = call float @llvm.amdgcn.rcp.f32(float %sqrt)
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78 store float %rcp, float addrspace(1)* %out, align 4
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79 ret void
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80 }
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81
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82 ; FUNC-LABEL: {{^}}rcp_f64:
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83 ; SI: v_rcp_f64_e32 [[RESULT:v\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}
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84 ; SI-NOT: [[RESULT]]
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85 ; SI: buffer_store_dwordx2 [[RESULT]]
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86 define amdgpu_kernel void @rcp_f64(double addrspace(1)* %out, double %src) #1 {
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87 %rcp = call double @llvm.amdgcn.rcp.f64(double %src)
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88 store double %rcp, double addrspace(1)* %out, align 8
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89 ret void
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90 }
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91
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92 ; FUNC-LABEL: {{^}}unsafe_rcp_f64:
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93 ; SI: v_rcp_f64_e32 [[RESULT:v\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}
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94 ; SI-NOT: [[RESULT]]
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95 ; SI: buffer_store_dwordx2 [[RESULT]]
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96 define amdgpu_kernel void @unsafe_rcp_f64(double addrspace(1)* %out, double %src) #2 {
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97 %rcp = call double @llvm.amdgcn.rcp.f64(double %src)
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98 store double %rcp, double addrspace(1)* %out, align 8
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99 ret void
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100 }
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101
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102 ; FUNC-LABEL: {{^}}rcp_pat_f64:
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103 ; SI: v_div_scale_f64
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104 define amdgpu_kernel void @rcp_pat_f64(double addrspace(1)* %out, double %src) #1 {
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105 %rcp = fdiv double 1.0, %src
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106 store double %rcp, double addrspace(1)* %out, align 8
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107 ret void
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108 }
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109
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110 ; FUNC-LABEL: {{^}}unsafe_rcp_pat_f64:
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111 ; SI: v_rcp_f64_e32 [[RESULT:v\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}
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112 ; SI-NOT: [[RESULT]]
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113 ; SI: buffer_store_dwordx2 [[RESULT]]
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114 define amdgpu_kernel void @unsafe_rcp_pat_f64(double addrspace(1)* %out, double %src) #2 {
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115 %rcp = fdiv double 1.0, %src
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116 store double %rcp, double addrspace(1)* %out, align 8
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117 ret void
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118 }
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119
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120 ; FUNC-LABEL: {{^}}safe_rsq_rcp_pat_f64:
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121 ; SI-NOT: v_rsq_f64_e32
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122 ; SI: v_sqrt_f64
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123 ; SI: v_rcp_f64
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124 define amdgpu_kernel void @safe_rsq_rcp_pat_f64(double addrspace(1)* %out, double %src) #1 {
120
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125 %sqrt = call double @llvm.sqrt.f64(double %src)
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126 %rcp = call double @llvm.amdgcn.rcp.f64(double %sqrt)
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127 store double %rcp, double addrspace(1)* %out, align 8
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128 ret void
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129 }
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130
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131 ; FUNC-LABEL: {{^}}unsafe_rsq_rcp_pat_f64:
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132 ; SI: v_rsq_f64_e32 [[RESULT:v\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}
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133 ; SI-NOT: [[RESULT]]
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134 ; SI: buffer_store_dwordx2 [[RESULT]]
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135 define amdgpu_kernel void @unsafe_rsq_rcp_pat_f64(double addrspace(1)* %out, double %src) #2 {
120
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136 %sqrt = call double @llvm.sqrt.f64(double %src)
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137 %rcp = call double @llvm.amdgcn.rcp.f64(double %sqrt)
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138 store double %rcp, double addrspace(1)* %out, align 8
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139 ret void
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140 }
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141
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142 attributes #0 = { nounwind readnone }
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143 attributes #1 = { nounwind "unsafe-fp-math"="false" "target-features"="-fp32-denormals" }
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144 attributes #2 = { nounwind "unsafe-fp-math"="true" "target-features"="-fp32-denormals" }
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145 attributes #3 = { nounwind "unsafe-fp-math"="false" "target-features"="+fp32-denormals" }
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146 attributes #4 = { nounwind "unsafe-fp-math"="true" "target-features"="+fp32-denormals" }