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annotate test/CodeGen/AMDGPU/lshr.v2i16.ll @ 128:c347d3398279 default tip

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fix
author mir3636
date Wed, 06 Dec 2017 14:37:17 +0900
parents 803732b1fca8
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
121
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1 ; RUN: llc -march=amdgcn -mcpu=gfx901 -verify-machineinstrs -enable-packed-inlinable-literals < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s
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2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=CIVI %s
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3 ; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=CIVI %s
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4
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5 ; GCN-LABEL: {{^}}s_lshr_v2i16:
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6 ; GFX9: s_load_dword [[LHS:s[0-9]+]]
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7 ; GFX9: s_load_dword [[RHS:s[0-9]+]]
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8 ; GFX9: v_mov_b32_e32 [[VLHS:v[0-9]+]], [[LHS]]
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9 ; GFX9: v_pk_lshrrev_b16 [[RESULT:v[0-9]+]], [[RHS]], [[VLHS]]
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10
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11 ; VI: v_lshrrev_b32_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
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12 ; CI: v_lshrrev_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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13 ; CI-DAG: v_lshlrev_b32_e32 v{{[0-9]+}}, 16, v{{[0-9]+}}
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14 ; CIVI-DAG: v_bfe_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, 16
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15 ; CIVI: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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16 define amdgpu_kernel void @s_lshr_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> %lhs, <2 x i16> %rhs) #0 {
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17 %result = lshr <2 x i16> %lhs, %rhs
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18 store <2 x i16> %result, <2 x i16> addrspace(1)* %out
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19 ret void
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20 }
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21
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22 ; GCN-LABEL: {{^}}v_lshr_v2i16:
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23 ; GCN: {{buffer|flat|global}}_load_dword [[LHS:v[0-9]+]]
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24 ; GCN: {{buffer|flat|global}}_load_dword [[RHS:v[0-9]+]]
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25 ; GFX9: v_pk_lshrrev_b16 [[RESULT:v[0-9]+]], [[RHS]], [[LHS]]
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26
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27 ; VI: v_lshrrev_b16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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28 ; VI: v_lshrrev_b16_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
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29 ; VI: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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30
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31 ; CI: s_mov_b32 [[MASK:s[0-9]+]], 0xffff{{$}}
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32 ; CI-DAG: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, [[LHS]]
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33 ; CI-DAG: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, [[RHS]]
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34 ; CI: v_and_b32_e32 v{{[0-9]+}}, [[MASK]], v{{[0-9]+}}
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35 ; CI: v_and_b32_e32 v{{[0-9]+}}, [[MASK]], v{{[0-9]+}}
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36 ; CI: v_bfe_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, 16
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37 ; CI: v_lshrrev_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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38 ; CI: v_lshlrev_b32_e32 v{{[0-9]+}}, 16, v{{[0-9]+}}
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39 ; CI: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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40 define amdgpu_kernel void @v_lshr_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 {
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41 %tid = call i32 @llvm.amdgcn.workitem.id.x()
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42 %tid.ext = sext i32 %tid to i64
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43 %in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext
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44 %out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext
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45 %b_ptr = getelementptr <2 x i16>, <2 x i16> addrspace(1)* %in.gep, i32 1
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46 %a = load <2 x i16>, <2 x i16> addrspace(1)* %in.gep
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47 %b = load <2 x i16>, <2 x i16> addrspace(1)* %b_ptr
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48 %result = lshr <2 x i16> %a, %b
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49 store <2 x i16> %result, <2 x i16> addrspace(1)* %out.gep
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50 ret void
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51 }
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52
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53 ; GCN-LABEL: {{^}}lshr_v_s_v2i16:
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54 ; GFX9: s_load_dword [[RHS:s[0-9]+]]
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55 ; GFX9: {{buffer|flat|global}}_load_dword [[LHS:v[0-9]+]]
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56 ; GFX9: v_pk_lshrrev_b16 [[RESULT:v[0-9]+]], [[RHS]], [[LHS]]
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57 define amdgpu_kernel void @lshr_v_s_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in, <2 x i16> %sgpr) #0 {
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58 %tid = call i32 @llvm.amdgcn.workitem.id.x()
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59 %tid.ext = sext i32 %tid to i64
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60 %in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext
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61 %out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext
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62 %vgpr = load <2 x i16>, <2 x i16> addrspace(1)* %in.gep
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63 %result = lshr <2 x i16> %vgpr, %sgpr
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64 store <2 x i16> %result, <2 x i16> addrspace(1)* %out.gep
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65 ret void
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66 }
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67
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68 ; GCN-LABEL: {{^}}lshr_s_v_v2i16:
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69 ; GFX9: s_load_dword [[LHS:s[0-9]+]]
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70 ; GFX9: {{buffer|flat|global}}_load_dword [[RHS:v[0-9]+]]
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71 ; GFX9: v_pk_lshrrev_b16 [[RESULT:v[0-9]+]], [[RHS]], [[LHS]]
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72 define amdgpu_kernel void @lshr_s_v_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in, <2 x i16> %sgpr) #0 {
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73 %tid = call i32 @llvm.amdgcn.workitem.id.x()
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74 %tid.ext = sext i32 %tid to i64
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75 %in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext
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76 %out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext
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77 %vgpr = load <2 x i16>, <2 x i16> addrspace(1)* %in.gep
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78 %result = lshr <2 x i16> %sgpr, %vgpr
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79 store <2 x i16> %result, <2 x i16> addrspace(1)* %out.gep
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80 ret void
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81 }
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82
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83 ; GCN-LABEL: {{^}}lshr_imm_v_v2i16:
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84 ; GCN: {{buffer|flat|global}}_load_dword [[RHS:v[0-9]+]]
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85 ; GFX9: v_pk_lshrrev_b16 [[RESULT:v[0-9]+]], [[RHS]], 8
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86 define amdgpu_kernel void @lshr_imm_v_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 {
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87 %tid = call i32 @llvm.amdgcn.workitem.id.x()
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88 %tid.ext = sext i32 %tid to i64
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89 %in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext
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90 %out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext
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91 %vgpr = load <2 x i16>, <2 x i16> addrspace(1)* %in.gep
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92 %result = lshr <2 x i16> <i16 8, i16 8>, %vgpr
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93 store <2 x i16> %result, <2 x i16> addrspace(1)* %out.gep
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94 ret void
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95 }
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96
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97 ; GCN-LABEL: {{^}}lshr_v_imm_v2i16:
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98 ; GCN: {{buffer|flat|global}}_load_dword [[LHS:v[0-9]+]]
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99 ; GFX9: v_pk_lshrrev_b16 [[RESULT:v[0-9]+]], 8, [[LHS]]
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100 define amdgpu_kernel void @lshr_v_imm_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 {
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101 %tid = call i32 @llvm.amdgcn.workitem.id.x()
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102 %tid.ext = sext i32 %tid to i64
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103 %in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext
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104 %out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext
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105 %vgpr = load <2 x i16>, <2 x i16> addrspace(1)* %in.gep
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106 %result = lshr <2 x i16> %vgpr, <i16 8, i16 8>
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107 store <2 x i16> %result, <2 x i16> addrspace(1)* %out.gep
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108 ret void
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109 }
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110
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111 ; GCN-LABEL: {{^}}v_lshr_v4i16:
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112 ; GCN: {{buffer|flat|global}}_load_dwordx2
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113 ; GCN: {{buffer|flat|global}}_load_dwordx2
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114 ; GFX9: v_pk_lshrrev_b16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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115 ; GFX9: v_pk_lshrrev_b16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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116 ; GCN: {{buffer|flat|global}}_store_dwordx2
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117 define amdgpu_kernel void @v_lshr_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> addrspace(1)* %in) #0 {
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118 %tid = call i32 @llvm.amdgcn.workitem.id.x()
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119 %tid.ext = sext i32 %tid to i64
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120 %in.gep = getelementptr inbounds <4 x i16>, <4 x i16> addrspace(1)* %in, i64 %tid.ext
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121 %out.gep = getelementptr inbounds <4 x i16>, <4 x i16> addrspace(1)* %out, i64 %tid.ext
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122 %b_ptr = getelementptr <4 x i16>, <4 x i16> addrspace(1)* %in.gep, i32 1
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123 %a = load <4 x i16>, <4 x i16> addrspace(1)* %in.gep
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124 %b = load <4 x i16>, <4 x i16> addrspace(1)* %b_ptr
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125 %result = lshr <4 x i16> %a, %b
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126 store <4 x i16> %result, <4 x i16> addrspace(1)* %out.gep
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127 ret void
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128 }
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129
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130 ; GCN-LABEL: {{^}}lshr_v_imm_v4i16:
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131 ; GCN: {{buffer|flat|global}}_load_dwordx2
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132 ; GFX9: v_pk_lshrrev_b16 v{{[0-9]+}}, 8, v{{[0-9]+}}
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133 ; GFX9: v_pk_lshrrev_b16 v{{[0-9]+}}, 8, v{{[0-9]+}}
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134 ; GCN: {{buffer|flat|global}}_store_dwordx2
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135 define amdgpu_kernel void @lshr_v_imm_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> addrspace(1)* %in) #0 {
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136 %tid = call i32 @llvm.amdgcn.workitem.id.x()
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137 %tid.ext = sext i32 %tid to i64
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138 %in.gep = getelementptr inbounds <4 x i16>, <4 x i16> addrspace(1)* %in, i64 %tid.ext
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139 %out.gep = getelementptr inbounds <4 x i16>, <4 x i16> addrspace(1)* %out, i64 %tid.ext
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140 %vgpr = load <4 x i16>, <4 x i16> addrspace(1)* %in.gep
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141 %result = lshr <4 x i16> %vgpr, <i16 8, i16 8, i16 8, i16 8>
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142 store <4 x i16> %result, <4 x i16> addrspace(1)* %out.gep
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143 ret void
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144 }
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145
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146 declare i32 @llvm.amdgcn.workitem.id.x() #1
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147
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148 attributes #0 = { nounwind }
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149 attributes #1 = { nounwind readnone }