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annotate test/CodeGen/AMDGPU/mad_uint24.ll @ 128:c347d3398279 default tip

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fix
author mir3636
date Wed, 06 Dec 2017 14:37:17 +0900
parents 803732b1fca8
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
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1 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG --check-prefix=FUNC
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2 ; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=EG --check-prefix=FUNC
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3 ; RUN: llc < %s -march=amdgcn -verify-machineinstrs | FileCheck %s --check-prefix=SI --check-prefix=FUNC
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4 ; RUN: llc < %s -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s --check-prefix=VI --check-prefix=FUNC
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5 ; RUN: llc < %s -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s --check-prefix=VI --check-prefix=FUNC
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7 declare i32 @llvm.r600.read.tidig.x() nounwind readnone
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8
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9 ; FUNC-LABEL: {{^}}u32_mad24:
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10 ; EG: MULADD_UINT24
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11 ; SI: v_mad_u32_u24
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12 ; VI: v_mad_u32_u24
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13
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14 define amdgpu_kernel void @u32_mad24(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) {
0
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15 entry:
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16 %0 = shl i32 %a, 8
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17 %a_24 = lshr i32 %0, 8
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18 %1 = shl i32 %b, 8
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19 %b_24 = lshr i32 %1, 8
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20 %2 = mul i32 %a_24, %b_24
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21 %3 = add i32 %2, %c
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22 store i32 %3, i32 addrspace(1)* %out
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23 ret void
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24 }
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25
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26 ; FUNC-LABEL: {{^}}i16_mad24:
0
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27 ; The order of A and B does not matter.
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28 ; EG: MULADD_UINT24 {{[* ]*}}T{{[0-9]}}.[[MAD_CHAN:[XYZW]]]
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29 ; The result must be sign-extended
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30 ; EG: BFE_INT {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[MAD_CHAN]], 0.0, literal.x
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31 ; EG: 16
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32 ; FIXME: Should be using scalar instructions here.
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33 ; GCN: v_mad_u32_u24 [[MAD:v[0-9]]], {{[sv][0-9], [sv][0-9]}}
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34 ; GCN: v_bfe_i32 v{{[0-9]}}, [[MAD]], 0, 16
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35 define amdgpu_kernel void @i16_mad24(i32 addrspace(1)* %out, i16 %a, i16 %b, i16 %c) {
0
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36 entry:
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37 %0 = mul i16 %a, %b
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38 %1 = add i16 %0, %c
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39 %2 = sext i16 %1 to i32
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40 store i32 %2, i32 addrspace(1)* %out
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41 ret void
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42 }
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43
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44 ; FIXME: Need to handle non-uniform case for function below (load without gep).
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45 ; FUNC-LABEL: {{^}}i8_mad24:
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46 ; EG: MULADD_UINT24 {{[* ]*}}T{{[0-9]}}.[[MAD_CHAN:[XYZW]]]
0
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47 ; The result must be sign-extended
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48 ; EG: BFE_INT {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[MAD_CHAN]], 0.0, literal.x
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49 ; EG: 8
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50 ; GCN: v_mad_u32_u24 [[MUL:v[0-9]]], {{[sv][0-9], [sv][0-9]}}
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51 ; GCN: v_bfe_i32 v{{[0-9]}}, [[MUL]], 0, 8
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52 define amdgpu_kernel void @i8_mad24(i32 addrspace(1)* %out, i8 %a, i8 %b, i8 %c) {
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53 entry:
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54 %0 = mul i8 %a, %b
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55 %1 = add i8 %0, %c
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56 %2 = sext i8 %1 to i32
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57 store i32 %2, i32 addrspace(1)* %out
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58 ret void
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59 }
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61 ; This tests for a bug where the mad_u24 pattern matcher would call
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62 ; SimplifyDemandedBits on the first operand of the mul instruction
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63 ; assuming that the pattern would be matched to a 24-bit mad. This
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64 ; led to some instructions being incorrectly erased when the entire
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65 ; 24-bit mad pattern wasn't being matched.
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66
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67 ; Check that the select instruction is not deleted.
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68 ; FUNC-LABEL: {{^}}i24_i32_i32_mad:
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69 ; EG: CNDE_INT
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70 ; SI: v_cndmask
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71 define amdgpu_kernel void @i24_i32_i32_mad(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c, i32 %d) {
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72 entry:
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73 %0 = ashr i32 %a, 8
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74 %1 = icmp ne i32 %c, 0
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75 %2 = select i1 %1, i32 %0, i32 34
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76 %3 = mul i32 %2, %c
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77 %4 = add i32 %3, %d
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78 store i32 %4, i32 addrspace(1)* %out
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79 ret void
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80 }
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81
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82 ; FUNC-LABEL: {{^}}extra_and:
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83 ; SI-NOT: v_and
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84 ; SI: v_mad_u32_u24
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85 ; SI: v_mad_u32_u24
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86 define amdgpu_kernel void @extra_and(i32 addrspace(1)* %arg, i32 %arg2, i32 %arg3) {
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87 bb:
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88 br label %bb4
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89
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90 bb4: ; preds = %bb4, %bb
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91 %tmp = phi i32 [ 0, %bb ], [ %tmp13, %bb4 ]
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92 %tmp5 = phi i32 [ 0, %bb ], [ %tmp13, %bb4 ]
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93 %tmp6 = phi i32 [ 0, %bb ], [ %tmp15, %bb4 ]
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94 %tmp7 = phi i32 [ 0, %bb ], [ %tmp15, %bb4 ]
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95 %tmp8 = and i32 %tmp7, 16777215
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96 %tmp9 = and i32 %tmp6, 16777215
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97 %tmp10 = and i32 %tmp5, 16777215
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98 %tmp11 = and i32 %tmp, 16777215
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99 %tmp12 = mul i32 %tmp8, %tmp11
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100 %tmp13 = add i32 %arg2, %tmp12
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101 %tmp14 = mul i32 %tmp9, %tmp11
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102 %tmp15 = add i32 %arg3, %tmp14
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103 %tmp16 = add nuw nsw i32 %tmp13, %tmp15
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104 %tmp17 = icmp eq i32 %tmp16, 8
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105 br i1 %tmp17, label %bb18, label %bb4
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106
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107 bb18: ; preds = %bb4
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108 store i32 %tmp16, i32 addrspace(1)* %arg
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109 ret void
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110 }
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111
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112 ; FUNC-LABEL: {{^}}dont_remove_shift
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113 ; SI: v_lshr
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114 ; SI: v_mad_u32_u24
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115 ; SI: v_mad_u32_u24
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116 define amdgpu_kernel void @dont_remove_shift(i32 addrspace(1)* %arg, i32 %arg2, i32 %arg3) {
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117 bb:
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118 br label %bb4
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119
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120 bb4: ; preds = %bb4, %bb
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121 %tmp = phi i32 [ 0, %bb ], [ %tmp13, %bb4 ]
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122 %tmp5 = phi i32 [ 0, %bb ], [ %tmp13, %bb4 ]
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123 %tmp6 = phi i32 [ 0, %bb ], [ %tmp15, %bb4 ]
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124 %tmp7 = phi i32 [ 0, %bb ], [ %tmp15, %bb4 ]
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125 %tmp8 = lshr i32 %tmp7, 8
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126 %tmp9 = lshr i32 %tmp6, 8
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127 %tmp10 = lshr i32 %tmp5, 8
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128 %tmp11 = lshr i32 %tmp, 8
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129 %tmp12 = mul i32 %tmp8, %tmp11
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130 %tmp13 = add i32 %arg2, %tmp12
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131 %tmp14 = mul i32 %tmp9, %tmp11
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132 %tmp15 = add i32 %arg3, %tmp14
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133 %tmp16 = add nuw nsw i32 %tmp13, %tmp15
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134 %tmp17 = icmp eq i32 %tmp16, 8
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135 br i1 %tmp17, label %bb18, label %bb4
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136
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137 bb18: ; preds = %bb4
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138 store i32 %tmp16, i32 addrspace(1)* %arg
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139 ret void
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
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140 }