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annotate test/CodeGen/AMDGPU/madak.ll @ 128:c347d3398279 default tip

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fix
author mir3636
date Wed, 06 Dec 2017 14:37:17 +0900
parents 803732b1fca8
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
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1 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s
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2 ; XUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN %s
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3
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4 ; FIXME: Enable VI
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5
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6 declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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7 declare float @llvm.fabs.f32(float) nounwind readnone
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8
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9 ; GCN-LABEL: {{^}}madak_f32:
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10 ; GCN: buffer_load_dword [[VA:v[0-9]+]]
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11 ; GCN: buffer_load_dword [[VB:v[0-9]+]]
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12 ; GCN: v_madak_f32 {{v[0-9]+}}, [[VA]], [[VB]], 0x41200000
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13 define amdgpu_kernel void @madak_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in.a, float addrspace(1)* noalias %in.b) nounwind {
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14 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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15 %in.a.gep = getelementptr float, float addrspace(1)* %in.a, i32 %tid
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16 %in.b.gep = getelementptr float, float addrspace(1)* %in.b, i32 %tid
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17 %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid
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18
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19 %a = load float, float addrspace(1)* %in.a.gep, align 4
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20 %b = load float, float addrspace(1)* %in.b.gep, align 4
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21
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22 %mul = fmul float %a, %b
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23 %madak = fadd float %mul, 10.0
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24 store float %madak, float addrspace(1)* %out.gep, align 4
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25 ret void
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26 }
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27
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28 ; Make sure this is only folded with one use. This is a code size
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29 ; optimization and if we fold the immediate multiple times, we'll undo
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30 ; it.
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31
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32 ; GCN-LABEL: {{^}}madak_2_use_f32:
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33 ; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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34 ; GCN-DAG: buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
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35 ; GCN-DAG: buffer_load_dword [[VC:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8
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36 ; GCN-DAG: v_mov_b32_e32 [[VK:v[0-9]+]], 0x41200000
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37 ; GCN-DAG: v_madak_f32 {{v[0-9]+}}, [[VA]], [[VB]], 0x41200000
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38 ; GCN-DAG: v_mac_f32_e32 [[VK]], [[VA]], [[VC]]
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39 ; GCN: s_endpgm
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40 define amdgpu_kernel void @madak_2_use_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) nounwind {
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41 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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42
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43 %in.gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
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44 %in.gep.1 = getelementptr float, float addrspace(1)* %in.gep.0, i32 1
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45 %in.gep.2 = getelementptr float, float addrspace(1)* %in.gep.0, i32 2
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46
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47 %out.gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
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48 %out.gep.1 = getelementptr float, float addrspace(1)* %in.gep.0, i32 1
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49
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50 %a = load volatile float, float addrspace(1)* %in.gep.0, align 4
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51 %b = load volatile float, float addrspace(1)* %in.gep.1, align 4
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52 %c = load volatile float, float addrspace(1)* %in.gep.2, align 4
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53
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54 %mul0 = fmul float %a, %b
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55 %mul1 = fmul float %a, %c
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56 %madak0 = fadd float %mul0, 10.0
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57 %madak1 = fadd float %mul1, 10.0
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58
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59 store volatile float %madak0, float addrspace(1)* %out.gep.0, align 4
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60 store volatile float %madak1, float addrspace(1)* %out.gep.1, align 4
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61 ret void
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62 }
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63
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64 ; GCN-LABEL: {{^}}madak_m_inline_imm_f32:
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65 ; GCN: buffer_load_dword [[VA:v[0-9]+]]
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66 ; GCN: v_madak_f32 {{v[0-9]+}}, 4.0, [[VA]], 0x41200000
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67 define amdgpu_kernel void @madak_m_inline_imm_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in.a) nounwind {
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68 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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69 %in.a.gep = getelementptr float, float addrspace(1)* %in.a, i32 %tid
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70 %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid
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71
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72 %a = load float, float addrspace(1)* %in.a.gep, align 4
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73
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74 %mul = fmul float 4.0, %a
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75 %madak = fadd float %mul, 10.0
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76 store float %madak, float addrspace(1)* %out.gep, align 4
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77 ret void
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78 }
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79
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80 ; Make sure nothing weird happens with a value that is also allowed as
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81 ; an inline immediate.
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82
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83 ; GCN-LABEL: {{^}}madak_inline_imm_f32:
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84 ; GCN: buffer_load_dword [[VA:v[0-9]+]]
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85 ; GCN: buffer_load_dword [[VB:v[0-9]+]]
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86 ; GCN: v_mad_f32 {{v[0-9]+}}, [[VA]], [[VB]], 4.0
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87 define amdgpu_kernel void @madak_inline_imm_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in.a, float addrspace(1)* noalias %in.b) nounwind {
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88 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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89 %in.a.gep = getelementptr float, float addrspace(1)* %in.a, i32 %tid
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90 %in.b.gep = getelementptr float, float addrspace(1)* %in.b, i32 %tid
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91 %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid
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92
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93 %a = load float, float addrspace(1)* %in.a.gep, align 4
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94 %b = load float, float addrspace(1)* %in.b.gep, align 4
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95
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96 %mul = fmul float %a, %b
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97 %madak = fadd float %mul, 4.0
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98 store float %madak, float addrspace(1)* %out.gep, align 4
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99 ret void
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100 }
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101
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102 ; We can't use an SGPR when forming madak
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103 ; GCN-LABEL: {{^}}s_v_madak_f32:
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104 ; GCN-DAG: s_load_dword [[SB:s[0-9]+]]
95
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105 ; GCN-DAG: v_mov_b32_e32 [[VK:v[0-9]+]], 0x41200000
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106 ; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]]
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107 ; GCN-NOT: v_madak_f32
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108 ; GCN: v_mac_f32_e32 [[VK]], [[SB]], [[VA]]
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109 define amdgpu_kernel void @s_v_madak_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in.a, float %b) nounwind {
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110 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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111 %in.a.gep = getelementptr float, float addrspace(1)* %in.a, i32 %tid
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112 %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid
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113
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114 %a = load float, float addrspace(1)* %in.a.gep, align 4
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115
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116 %mul = fmul float %a, %b
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117 %madak = fadd float %mul, 10.0
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118 store float %madak, float addrspace(1)* %out.gep, align 4
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119 ret void
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parents:
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120 }
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parents:
diff changeset
121
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122 ; GCN-LABEL: @v_s_madak_f32
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parents:
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123 ; GCN-DAG: s_load_dword [[SB:s[0-9]+]]
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124 ; GCN-DAG: v_mov_b32_e32 [[VK:v[0-9]+]], 0x41200000
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125 ; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]]
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126 ; GCN-NOT: v_madak_f32
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127 ; GCN: v_mac_f32_e32 [[VK]], [[SB]], [[VA]]
121
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128 define amdgpu_kernel void @v_s_madak_f32(float addrspace(1)* noalias %out, float %a, float addrspace(1)* noalias %in.b) nounwind {
120
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129 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
95
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130 %in.b.gep = getelementptr float, float addrspace(1)* %in.b, i32 %tid
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131 %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid
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132
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133 %b = load float, float addrspace(1)* %in.b.gep, align 4
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134
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135 %mul = fmul float %a, %b
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136 %madak = fadd float %mul, 10.0
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137 store float %madak, float addrspace(1)* %out.gep, align 4
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138 ret void
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139 }
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140
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141 ; GCN-LABEL: {{^}}s_s_madak_f32:
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142 ; GCN-NOT: v_madak_f32
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143 ; GCN: v_mac_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
121
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diff changeset
144 define amdgpu_kernel void @s_s_madak_f32(float addrspace(1)* %out, float %a, float %b) nounwind {
95
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145 %mul = fmul float %a, %b
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146 %madak = fadd float %mul, 10.0
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147 store float %madak, float addrspace(1)* %out, align 4
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148 ret void
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149 }
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150
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151 ; GCN-LABEL: {{^}}no_madak_src0_modifier_f32:
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152 ; GCN: buffer_load_dword [[VA:v[0-9]+]]
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153 ; GCN: buffer_load_dword [[VB:v[0-9]+]]
121
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154 ; GCN: v_mad_f32 {{v[0-9]+}}, |{{v[0-9]+}}|, {{v[0-9]+}}, {{[sv][0-9]+}}
95
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155 ; GCN: s_endpgm
121
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156 define amdgpu_kernel void @no_madak_src0_modifier_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in.a, float addrspace(1)* noalias %in.b) nounwind {
120
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157 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
95
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158 %in.a.gep = getelementptr float, float addrspace(1)* %in.a, i32 %tid
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159 %in.b.gep = getelementptr float, float addrspace(1)* %in.b, i32 %tid
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160 %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid
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diff changeset
161
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162 %a = load float, float addrspace(1)* %in.a.gep, align 4
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163 %b = load float, float addrspace(1)* %in.b.gep, align 4
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164
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165 %a.fabs = call float @llvm.fabs.f32(float %a) nounwind readnone
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diff changeset
166
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167 %mul = fmul float %a.fabs, %b
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168 %madak = fadd float %mul, 10.0
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169 store float %madak, float addrspace(1)* %out.gep, align 4
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170 ret void
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parents:
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171 }
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diff changeset
172
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173 ; GCN-LABEL: {{^}}no_madak_src1_modifier_f32:
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parents:
diff changeset
174 ; GCN: buffer_load_dword [[VA:v[0-9]+]]
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175 ; GCN: buffer_load_dword [[VB:v[0-9]+]]
121
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176 ; GCN: v_mad_f32 {{v[0-9]+}}, {{v[0-9]+}}, |{{v[0-9]+}}|, {{[sv][0-9]+}}
95
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177 ; GCN: s_endpgm
121
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178 define amdgpu_kernel void @no_madak_src1_modifier_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in.a, float addrspace(1)* noalias %in.b) nounwind {
120
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179 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
95
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180 %in.a.gep = getelementptr float, float addrspace(1)* %in.a, i32 %tid
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181 %in.b.gep = getelementptr float, float addrspace(1)* %in.b, i32 %tid
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diff changeset
182 %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid
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diff changeset
183
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diff changeset
184 %a = load float, float addrspace(1)* %in.a.gep, align 4
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diff changeset
185 %b = load float, float addrspace(1)* %in.b.gep, align 4
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parents:
diff changeset
186
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diff changeset
187 %b.fabs = call float @llvm.fabs.f32(float %b) nounwind readnone
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parents:
diff changeset
188
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diff changeset
189 %mul = fmul float %a, %b.fabs
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diff changeset
190 %madak = fadd float %mul, 10.0
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parents:
diff changeset
191 store float %madak, float addrspace(1)* %out.gep, align 4
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parents:
diff changeset
192 ret void
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parents:
diff changeset
193 }
120
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diff changeset
194
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195 ; SIFoldOperands should not fold the SGPR copy into the instruction
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196 ; because the implicit immediate already uses the constant bus.
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197 ; GCN-LABEL: {{^}}madak_constant_bus_violation:
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198 ; GCN: s_load_dword [[SGPR0:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, {{0xa|0x28}}
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diff changeset
199 ; GCN: v_mov_b32_e32 [[SGPR0_VCOPY:v[0-9]+]], [[SGPR0]]
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diff changeset
200 ; GCN: buffer_load_dword [[VGPR:v[0-9]+]]
121
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diff changeset
201 ; GCN: v_madak_f32 [[MADAK:v[0-9]+]], 0.5, [[SGPR0_VCOPY]], 0x42280000
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kono
parents: 120
diff changeset
202 ; GCN: v_mul_f32_e32 [[MUL:v[0-9]+]], [[MADAK]], [[VGPR]]
120
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diff changeset
203 ; GCN: buffer_store_dword [[MUL]]
121
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diff changeset
204 define amdgpu_kernel void @madak_constant_bus_violation(i32 %arg1, float %sgpr0, float %sgpr1) #0 {
120
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diff changeset
205 bb:
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206 %tmp = icmp eq i32 %arg1, 0
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diff changeset
207 br i1 %tmp, label %bb3, label %bb4
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diff changeset
208
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diff changeset
209 bb3:
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diff changeset
210 store volatile float 0.0, float addrspace(1)* undef
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diff changeset
211 br label %bb4
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diff changeset
212
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diff changeset
213 bb4:
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diff changeset
214 %vgpr = load volatile float, float addrspace(1)* undef
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diff changeset
215 %tmp0 = fmul float %sgpr0, 0.5
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diff changeset
216 %tmp1 = fadd float %tmp0, 42.0
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diff changeset
217 %tmp2 = fmul float %tmp1, %vgpr
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diff changeset
218 store volatile float %tmp2, float addrspace(1)* undef, align 4
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219 ret void
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220 }
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diff changeset
221
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diff changeset
222 attributes #0 = { nounwind}