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annotate test/CodeGen/AMDGPU/movrels-bug.mir @ 128:c347d3398279 default tip

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fix
author mir3636
date Wed, 06 Dec 2017 14:37:17 +0900
parents 803732b1fca8
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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121
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1 # RUN: llc -march=amdgcn -verify-machineinstrs -run-pass post-RA-sched %s -o - | FileCheck %s
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2
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3 # This tests a situation where a sub-register of a killed super-register operand
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4 # of V_MOVRELS happens to have an undef use later on. This leads to the post RA
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5 # scheduler adding additional implicit operands to the V_MOVRELS, which used
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6 # to fail machine instruction verification.
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7
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8 --- |
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9
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10 define amdgpu_vs void @main(i32 %arg) { ret void }
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11
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12 ...
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13 ---
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14 # CHECK-LABEL: name: main
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15 # CHECK-LABEL: bb.0:
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16 # CHECK: V_MOVRELS_B32_e32
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17 # CHECK: V_MAC_F32_e32
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18
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19 name: main
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20 tracksRegLiveness: true
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21 body: |
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22 bb.0:
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23 %m0 = S_MOV_B32 undef %sgpr0
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24 V_MOVRELD_B32_e32 undef %vgpr2, 0, implicit %m0, implicit %exec, implicit-def %vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8, implicit undef %vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8(tied-def 4)
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25 %m0 = S_MOV_B32 undef %sgpr0
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26 %vgpr1 = V_MOVRELS_B32_e32 undef %vgpr1, implicit %m0, implicit %exec, implicit killed %vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8
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27 %vgpr4 = V_MAC_F32_e32 undef %vgpr0, undef %vgpr0, undef %vgpr4, implicit %exec
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28 EXP_DONE 15, undef %vgpr0, killed %vgpr1, killed %vgpr4, undef %vgpr0, 0, 0, 12, implicit %exec
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29 S_ENDPGM
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30
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31 ...