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annotate test/CodeGen/AMDGPU/mul.ll @ 128:c347d3398279 default tip

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fix
author mir3636
date Wed, 06 Dec 2017 14:37:17 +0900
parents 803732b1fca8
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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1 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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2 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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3 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG %s -check-prefix=FUNC
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5 ; mul24 and mad24 are affected
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6
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7 ; FUNC-LABEL: {{^}}test_mul_v2i32:
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8 ; EG: MULLO_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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9 ; EG: MULLO_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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10
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11 ; SI: v_mul_lo_i32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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12 ; SI: v_mul_lo_i32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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13
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14 define amdgpu_kernel void @test_mul_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
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15 %b_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 1
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16 %a = load <2 x i32>, <2 x i32> addrspace(1) * %in
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17 %b = load <2 x i32>, <2 x i32> addrspace(1) * %b_ptr
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18 %result = mul <2 x i32> %a, %b
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19 store <2 x i32> %result, <2 x i32> addrspace(1)* %out
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20 ret void
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21 }
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22
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23 ; FUNC-LABEL: {{^}}v_mul_v4i32:
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24 ; EG: MULLO_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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25 ; EG: MULLO_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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26 ; EG: MULLO_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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27 ; EG: MULLO_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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28
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29 ; SI: v_mul_lo_i32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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30 ; SI: v_mul_lo_i32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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31 ; SI: v_mul_lo_i32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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32 ; SI: v_mul_lo_i32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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33
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34 define amdgpu_kernel void @v_mul_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
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35 %b_ptr = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %in, i32 1
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36 %a = load <4 x i32>, <4 x i32> addrspace(1) * %in
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37 %b = load <4 x i32>, <4 x i32> addrspace(1) * %b_ptr
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38 %result = mul <4 x i32> %a, %b
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39 store <4 x i32> %result, <4 x i32> addrspace(1)* %out
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40 ret void
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41 }
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42
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43 ; FUNC-LABEL: {{^}}s_trunc_i64_mul_to_i32:
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44 ; SI: s_load_dword
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45 ; SI: s_load_dword
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46 ; SI: s_mul_i32
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47 ; SI: buffer_store_dword
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48 define amdgpu_kernel void @s_trunc_i64_mul_to_i32(i32 addrspace(1)* %out, i64 %a, i64 %b) {
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49 %mul = mul i64 %b, %a
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50 %trunc = trunc i64 %mul to i32
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51 store i32 %trunc, i32 addrspace(1)* %out, align 8
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52 ret void
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53 }
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54
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55 ; FUNC-LABEL: {{^}}v_trunc_i64_mul_to_i32:
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56 ; SI: s_load_dword
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57 ; SI: s_load_dword
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58 ; SI: v_mul_lo_i32
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59 ; SI: buffer_store_dword
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60 define amdgpu_kernel void @v_trunc_i64_mul_to_i32(i32 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) nounwind {
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61 %a = load i64, i64 addrspace(1)* %aptr, align 8
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62 %b = load i64, i64 addrspace(1)* %bptr, align 8
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63 %mul = mul i64 %b, %a
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64 %trunc = trunc i64 %mul to i32
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65 store i32 %trunc, i32 addrspace(1)* %out, align 8
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66 ret void
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67 }
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68
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69 ; This 64-bit multiply should just use MUL_HI and MUL_LO, since the top
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70 ; 32-bits of both arguments are sign bits.
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71 ; FUNC-LABEL: {{^}}mul64_sext_c:
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72 ; EG-DAG: MULLO_INT
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73 ; EG-DAG: MULHI_INT
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74 ; SI-DAG: s_mul_i32
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75 ; SI-DAG: v_mul_hi_i32
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76 define amdgpu_kernel void @mul64_sext_c(i64 addrspace(1)* %out, i32 %in) {
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77 entry:
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78 %0 = sext i32 %in to i64
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79 %1 = mul i64 %0, 80
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80 store i64 %1, i64 addrspace(1)* %out
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81 ret void
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82 }
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83
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84 ; FUNC-LABEL: {{^}}v_mul64_sext_c:
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85 ; EG-DAG: MULLO_INT
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86 ; EG-DAG: MULHI_INT
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87 ; SI-DAG: v_mul_lo_i32
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88 ; SI-DAG: v_mul_hi_i32
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89 ; SI: s_endpgm
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90 define amdgpu_kernel void @v_mul64_sext_c(i64 addrspace(1)* %out, i32 addrspace(1)* %in) {
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91 %val = load i32, i32 addrspace(1)* %in, align 4
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92 %ext = sext i32 %val to i64
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93 %mul = mul i64 %ext, 80
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94 store i64 %mul, i64 addrspace(1)* %out, align 8
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95 ret void
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96 }
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97
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98 ; FUNC-LABEL: {{^}}v_mul64_sext_inline_imm:
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99 ; SI-DAG: v_mul_lo_i32 v{{[0-9]+}}, v{{[0-9]+}}, 9
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100 ; SI-DAG: v_mul_hi_i32 v{{[0-9]+}}, v{{[0-9]+}}, 9
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101 ; SI: s_endpgm
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102 define amdgpu_kernel void @v_mul64_sext_inline_imm(i64 addrspace(1)* %out, i32 addrspace(1)* %in) {
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103 %val = load i32, i32 addrspace(1)* %in, align 4
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104 %ext = sext i32 %val to i64
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105 %mul = mul i64 %ext, 9
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106 store i64 %mul, i64 addrspace(1)* %out, align 8
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107 ret void
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108 }
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109
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110 ; FUNC-LABEL: {{^}}s_mul_i32:
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111 ; SI: s_load_dword [[SRC0:s[0-9]+]],
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112 ; SI: s_load_dword [[SRC1:s[0-9]+]],
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113 ; SI: s_mul_i32 [[SRESULT:s[0-9]+]], [[SRC0]], [[SRC1]]
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114 ; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[SRESULT]]
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115 ; SI: buffer_store_dword [[VRESULT]],
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116 ; SI: s_endpgm
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117 define amdgpu_kernel void @s_mul_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
95
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
118 %mul = mul i32 %a, %b
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
119 store i32 %mul, i32 addrspace(1)* %out, align 4
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
120 ret void
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
121 }
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
122
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
123 ; FUNC-LABEL: {{^}}v_mul_i32:
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
124 ; SI: v_mul_lo_i32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
121
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
125 define amdgpu_kernel void @v_mul_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
126 %b_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
127 %a = load i32, i32 addrspace(1)* %in
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
128 %b = load i32, i32 addrspace(1)* %b_ptr
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
129 %result = mul i32 %a, %b
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
130 store i32 %result, i32 addrspace(1)* %out
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
131 ret void
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
132 }
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
133
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
134 ; A standard 64-bit multiply. The expansion should be around 6 instructions.
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
135 ; It would be difficult to match the expansion correctly without writing
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
136 ; a really complicated list of FileCheck expressions. I don't want
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
137 ; to confuse people who may 'break' this test with a correct optimization,
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
138 ; so this test just uses FUNC-LABEL to make sure the compiler does not
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
139 ; crash with a 'failed to select' error.
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
140
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
141 ; FUNC-LABEL: {{^}}s_mul_i64:
121
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
142 define amdgpu_kernel void @s_mul_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
143 %mul = mul i64 %a, %b
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
144 store i64 %mul, i64 addrspace(1)* %out, align 8
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
145 ret void
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
146 }
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
147
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
148 ; FUNC-LABEL: {{^}}v_mul_i64:
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
149 ; SI: v_mul_lo_i32
121
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
150 define amdgpu_kernel void @v_mul_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) {
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
151 %a = load i64, i64 addrspace(1)* %aptr, align 8
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
152 %b = load i64, i64 addrspace(1)* %bptr, align 8
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
153 %mul = mul i64 %a, %b
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
154 store i64 %mul, i64 addrspace(1)* %out, align 8
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
155 ret void
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
156 }
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
157
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
158 ; FUNC-LABEL: {{^}}mul32_in_branch:
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
159 ; SI: s_mul_i32
121
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
160 define amdgpu_kernel void @mul32_in_branch(i32 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %a, i32 %b, i32 %c) {
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
161 entry:
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
162 %0 = icmp eq i32 %a, 0
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
163 br i1 %0, label %if, label %else
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
164
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
165 if:
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
166 %1 = load i32, i32 addrspace(1)* %in
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
167 br label %endif
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
168
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
169 else:
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
170 %2 = mul i32 %a, %b
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
171 br label %endif
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
172
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
173 endif:
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
174 %3 = phi i32 [%1, %if], [%2, %else]
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
175 store i32 %3, i32 addrspace(1)* %out
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
176 ret void
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
177 }
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
178
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
179 ; FUNC-LABEL: {{^}}mul64_in_branch:
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
180 ; SI-DAG: s_mul_i32
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
181 ; SI-DAG: v_mul_hi_u32
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
182 ; SI: s_endpgm
121
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
183 define amdgpu_kernel void @mul64_in_branch(i64 addrspace(1)* %out, i64 addrspace(1)* %in, i64 %a, i64 %b, i64 %c) {
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
184 entry:
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
185 %0 = icmp eq i64 %a, 0
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
186 br i1 %0, label %if, label %else
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
187
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
188 if:
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
189 %1 = load i64, i64 addrspace(1)* %in
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
190 br label %endif
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
191
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
192 else:
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
193 %2 = mul i64 %a, %b
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
194 br label %endif
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
195
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
196 endif:
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
197 %3 = phi i64 [%1, %if], [%2, %else]
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
198 store i64 %3, i64 addrspace(1)* %out
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
199 ret void
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
200 }
121
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
201
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
202 ; FIXME: Load dwordx4
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
203 ; FUNC-LABEL: {{^}}s_mul_i128:
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
204 ; SI: s_load_dwordx2
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
205 ; SI: s_load_dwordx2
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
206 ; SI: s_load_dwordx2
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
207 ; SI: s_load_dwordx2
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
208
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
209 ; SI: v_mul_hi_u32
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
210 ; SI: v_mul_hi_u32
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
211 ; SI: s_mul_i32
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
212 ; SI: v_mul_hi_u32
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
213 ; SI: s_mul_i32
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
214 ; SI-DAG: s_mul_i32
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
215 ; SI-DAG: v_mul_hi_u32
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
216 ; SI-DAG: v_mul_hi_u32
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
217 ; SI-DAG: s_mul_i32
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
218 ; SI-DAG: s_mul_i32
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
219 ; SI-DAG: v_mul_hi_u32
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
220 ; SI: s_mul_i32
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
221 ; SI: s_mul_i32
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
222 ; SI: s_mul_i32
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
223 ; SI: s_mul_i32
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
224 ; SI: s_mul_i32
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
225
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
226 ; SI: buffer_store_dwordx4
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
227 define amdgpu_kernel void @s_mul_i128(i128 addrspace(1)* %out, i128 %a, i128 %b) nounwind #0 {
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
228 %mul = mul i128 %a, %b
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
229 store i128 %mul, i128 addrspace(1)* %out
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
230 ret void
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
231 }
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
232
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
233 ; FUNC-LABEL: {{^}}v_mul_i128:
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
234 ; SI: {{buffer|flat}}_load_dwordx4
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
235 ; SI: {{buffer|flat}}_load_dwordx4
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
236
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
237 ; SI-DAG: v_mul_lo_i32
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
238 ; SI-DAG: v_mul_hi_u32
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
239 ; SI-DAG: v_mul_hi_u32
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
240 ; SI-DAG: v_mul_lo_i32
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
241 ; SI-DAG: v_mul_hi_u32
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
242 ; SI-DAG: v_mul_hi_u32
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
243 ; SI-DAG: v_mul_lo_i32
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
244 ; SI-DAG: v_mul_lo_i32
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
245 ; SI: v_add_i32_e32
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
246 ; SI-DAG: v_mul_hi_u32
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
247 ; SI-DAG: v_mul_lo_i32
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
248 ; SI-DAG: v_mul_hi_u32
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
249 ; SI-DAG: v_mul_lo_i32
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
250 ; SI-DAG: v_mul_lo_i32
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
251 ; SI-DAG: v_mul_lo_i32
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
252 ; SI-DAG: v_mul_lo_i32
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
253 ; SI-DAG: v_mul_lo_i32
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
254
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
255 ; SI: {{buffer|flat}}_store_dwordx4
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
256 define amdgpu_kernel void @v_mul_i128(i128 addrspace(1)* %out, i128 addrspace(1)* %aptr, i128 addrspace(1)* %bptr) #0 {
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
257 %tid = call i32 @llvm.r600.read.tidig.x()
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
258 %gep.a = getelementptr inbounds i128, i128 addrspace(1)* %aptr, i32 %tid
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
259 %gep.b = getelementptr inbounds i128, i128 addrspace(1)* %bptr, i32 %tid
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
260 %gep.out = getelementptr inbounds i128, i128 addrspace(1)* %bptr, i32 %tid
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
261 %a = load i128, i128 addrspace(1)* %gep.a
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
262 %b = load i128, i128 addrspace(1)* %gep.b
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
263 %mul = mul i128 %a, %b
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
264 store i128 %mul, i128 addrspace(1)* %gep.out
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
265 ret void
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
266 }
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
267
803732b1fca8 LLVM 5.0
kono
parents: 120
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268 declare i32 @llvm.r600.read.tidig.x() #1
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269
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270 attributes #0 = { nounwind }
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271 attributes #1 = { nounwind readnone}