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120
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1 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s
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121
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2 ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=FUNC %s
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120
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3
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4 declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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5 declare i32 @llvm.amdgcn.workitem.id.y() nounwind readnone
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6
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7 ; FUNC-LABEL: {{^}}test_umul24_i32:
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8 ; GCN: v_mul_u32_u24
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121
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9 define amdgpu_kernel void @test_umul24_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) {
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120
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10 entry:
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11 %0 = shl i32 %a, 8
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12 %a_24 = lshr i32 %0, 8
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13 %1 = shl i32 %b, 8
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14 %b_24 = lshr i32 %1, 8
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15 %2 = mul i32 %a_24, %b_24
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16 store i32 %2, i32 addrspace(1)* %out
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17 ret void
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18 }
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19
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20 ; FUNC-LABEL: {{^}}test_umul24_i16_sext:
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21 ; SI: v_mul_u32_u24_e{{(32|64)}} [[VI_MUL:v[0-9]]], {{[sv][0-9], [sv][0-9]}}
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22 ; SI: v_bfe_i32 v{{[0-9]}}, [[VI_MUL]], 0, 16
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23 ; VI: s_mul_i32 [[SI_MUL:s[0-9]]], s{{[0-9]}}, s{{[0-9]}}
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24 ; VI: s_sext_i32_i16 s{{[0-9]}}, [[SI_MUL]]
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121
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25 define amdgpu_kernel void @test_umul24_i16_sext(i32 addrspace(1)* %out, i16 %a, i16 %b) {
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120
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26 entry:
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27 %mul = mul i16 %a, %b
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28 %ext = sext i16 %mul to i32
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29 store i32 %ext, i32 addrspace(1)* %out
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30 ret void
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31 }
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32
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33 ; FUNC-LABEL: {{^}}test_umul24_i16_vgpr_sext:
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34 ; SI: v_mul_u32_u24_e{{(32|64)}} [[MUL:v[0-9]]], {{[sv][0-9], [sv][0-9]}}
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35 ; VI: v_mul_lo_u16_e{{(32|64)}} [[MUL:v[0-9]]], {{[sv][0-9], [sv][0-9]}}
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36 ; GCN: v_bfe_i32 v{{[0-9]}}, [[MUL]], 0, 16
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121
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37 define amdgpu_kernel void @test_umul24_i16_vgpr_sext(i32 addrspace(1)* %out, i16 addrspace(1)* %in) {
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120
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38 %tid.x = call i32 @llvm.amdgcn.workitem.id.x()
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39 %tid.y = call i32 @llvm.amdgcn.workitem.id.y()
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40 %ptr_a = getelementptr i16, i16 addrspace(1)* %in, i32 %tid.x
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41 %ptr_b = getelementptr i16, i16 addrspace(1)* %in, i32 %tid.y
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42 %a = load i16, i16 addrspace(1)* %ptr_a
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43 %b = load i16, i16 addrspace(1)* %ptr_b
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44 %mul = mul i16 %a, %b
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45 %val = sext i16 %mul to i32
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46 store i32 %val, i32 addrspace(1)* %out
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47 ret void
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48 }
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49
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50 ; FUNC-LABEL: {{^}}test_umul24_i16:
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51 ; SI: s_and_b32
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52 ; SI: v_mul_u32_u24_e32
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53 ; SI: v_and_b32_e32
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54 ; VI: s_mul_i32
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55 ; VI: s_and_b32
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56 ; VI: v_mov_b32_e32
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121
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57 define amdgpu_kernel void @test_umul24_i16(i32 addrspace(1)* %out, i16 %a, i16 %b) {
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120
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58 entry:
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59 %mul = mul i16 %a, %b
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60 %ext = zext i16 %mul to i32
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61 store i32 %ext, i32 addrspace(1)* %out
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62 ret void
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63 }
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64
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65 ; FUNC-LABEL: {{^}}test_umul24_i16_vgpr:
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66 ; SI: v_mul_u32_u24_e32
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67 ; SI: v_and_b32_e32
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68 ; VI: v_mul_lo_u16
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121
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69 define amdgpu_kernel void @test_umul24_i16_vgpr(i32 addrspace(1)* %out, i16 addrspace(1)* %in) {
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120
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70 %tid.x = call i32 @llvm.amdgcn.workitem.id.x()
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71 %tid.y = call i32 @llvm.amdgcn.workitem.id.y()
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72 %ptr_a = getelementptr i16, i16 addrspace(1)* %in, i32 %tid.x
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73 %ptr_b = getelementptr i16, i16 addrspace(1)* %in, i32 %tid.y
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74 %a = load i16, i16 addrspace(1)* %ptr_a
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75 %b = load i16, i16 addrspace(1)* %ptr_b
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76 %mul = mul i16 %a, %b
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77 %val = zext i16 %mul to i32
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78 store i32 %val, i32 addrspace(1)* %out
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79 ret void
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80 }
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81
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82 ; FUNC-LABEL: {{^}}test_umul24_i8_vgpr:
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83 ; SI: v_mul_u32_u24_e{{(32|64)}} [[MUL:v[0-9]]], {{[sv][0-9], [sv][0-9]}}
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84 ; VI: v_mul_lo_u16_e{{(32|64)}} [[MUL:v[0-9]]], {{[sv][0-9], [sv][0-9]}}
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85 ; GCN: v_bfe_i32 v{{[0-9]}}, [[MUL]], 0, 8
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121
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86 define amdgpu_kernel void @test_umul24_i8_vgpr(i32 addrspace(1)* %out, i8 addrspace(1)* %a, i8 addrspace(1)* %b) {
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120
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87 entry:
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88 %tid.x = call i32 @llvm.amdgcn.workitem.id.x()
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89 %tid.y = call i32 @llvm.amdgcn.workitem.id.y()
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90 %a.ptr = getelementptr i8, i8 addrspace(1)* %a, i32 %tid.x
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91 %b.ptr = getelementptr i8, i8 addrspace(1)* %b, i32 %tid.y
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92 %a.l = load i8, i8 addrspace(1)* %a.ptr
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93 %b.l = load i8, i8 addrspace(1)* %b.ptr
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94 %mul = mul i8 %a.l, %b.l
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95 %ext = sext i8 %mul to i32
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96 store i32 %ext, i32 addrspace(1)* %out
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97 ret void
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98 }
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99
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100 ; FUNC-LABEL: {{^}}test_umulhi24_i32_i64:
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101 ; GCN-NOT: and
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102 ; GCN: v_mul_hi_u32_u24_e32 [[RESULT:v[0-9]+]],
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103 ; GCN-NEXT: buffer_store_dword [[RESULT]]
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121
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104 define amdgpu_kernel void @test_umulhi24_i32_i64(i32 addrspace(1)* %out, i32 %a, i32 %b) {
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120
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105 entry:
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106 %a.24 = and i32 %a, 16777215
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107 %b.24 = and i32 %b, 16777215
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108 %a.24.i64 = zext i32 %a.24 to i64
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109 %b.24.i64 = zext i32 %b.24 to i64
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110 %mul48 = mul i64 %a.24.i64, %b.24.i64
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111 %mul48.hi = lshr i64 %mul48, 32
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112 %mul24hi = trunc i64 %mul48.hi to i32
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113 store i32 %mul24hi, i32 addrspace(1)* %out
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114 ret void
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115 }
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116
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117 ; FUNC-LABEL: {{^}}test_umulhi24:
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118 ; GCN-NOT: and
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119 ; GCN: v_mul_hi_u32_u24_e32 [[RESULT:v[0-9]+]],
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120 ; GCN-NEXT: buffer_store_dword [[RESULT]]
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121
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121 define amdgpu_kernel void @test_umulhi24(i32 addrspace(1)* %out, i64 %a, i64 %b) {
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120
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122 entry:
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123 %a.24 = and i64 %a, 16777215
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124 %b.24 = and i64 %b, 16777215
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125 %mul48 = mul i64 %a.24, %b.24
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126 %mul48.hi = lshr i64 %mul48, 32
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127 %mul24.hi = trunc i64 %mul48.hi to i32
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128 store i32 %mul24.hi, i32 addrspace(1)* %out
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129 ret void
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130 }
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131
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132 ; Multiply with 24-bit inputs and 64-bit output.
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133 ; FUNC-LABEL: {{^}}test_umul24_i64:
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134 ; GCN-NOT: and
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135 ; GCN-NOT: lshr
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136 ; GCN-DAG: v_mul_u32_u24_e32
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137 ; GCN-DAG: v_mul_hi_u32_u24_e32
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138 ; GCN: buffer_store_dwordx2
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121
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139 define amdgpu_kernel void @test_umul24_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) {
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120
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140 entry:
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141 %tmp0 = shl i64 %a, 40
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142 %a_24 = lshr i64 %tmp0, 40
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143 %tmp1 = shl i64 %b, 40
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144 %b_24 = lshr i64 %tmp1, 40
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145 %tmp2 = mul i64 %a_24, %b_24
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146 store i64 %tmp2, i64 addrspace(1)* %out
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147 ret void
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148 }
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149
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150 ; FUNC-LABEL: {{^}}test_umul24_i64_square:
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151 ; GCN: s_load_dword [[A:s[0-9]+]]
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152 ; GCN-NOT: s_and_b32
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153 ; GCN-DAG: v_mul_hi_u32_u24_e64 v{{[0-9]+}}, [[A]], [[A]]
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154 ; GCN-DAG: v_mul_u32_u24_e64 v{{[0-9]+}}, [[A]], [[A]]
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121
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155 define amdgpu_kernel void @test_umul24_i64_square(i64 addrspace(1)* %out, i64 %a) {
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120
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156 entry:
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157 %tmp0 = shl i64 %a, 40
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158 %a.24 = lshr i64 %tmp0, 40
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159 %tmp2 = mul i64 %a.24, %a.24
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160 store i64 %tmp2, i64 addrspace(1)* %out
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161 ret void
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162 }
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163
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164 ; FUNC-LABEL: {{^}}test_umulhi16_i32:
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165 ; GCN: s_and_b32
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166 ; GCN: s_and_b32
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167 ; GCN: v_mul_u32_u24_e32 [[MUL24:v[0-9]+]]
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168 ; GCN: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, [[MUL24]]
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121
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169 define amdgpu_kernel void @test_umulhi16_i32(i16 addrspace(1)* %out, i32 %a, i32 %b) {
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120
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170 entry:
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171 %a.16 = and i32 %a, 65535
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172 %b.16 = and i32 %b, 65535
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173 %mul = mul i32 %a.16, %b.16
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174 %hi = lshr i32 %mul, 16
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175 %mulhi = trunc i32 %hi to i16
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176 store i16 %mulhi, i16 addrspace(1)* %out
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177 ret void
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178 }
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179
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180 ; FUNC-LABEL: {{^}}test_umul24_i33:
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181 ; GCN: s_load_dword s
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182 ; GCN: s_load_dword s
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183 ; GCN-NOT: and
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184 ; GCN-NOT: lshr
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185 ; GCN-DAG: v_mul_u32_u24_e32 v[[MUL_LO:[0-9]+]],
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186 ; GCN-DAG: v_mul_hi_u32_u24_e32 v[[MUL_HI:[0-9]+]],
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187 ; GCN-DAG: v_and_b32_e32 v[[HI:[0-9]+]], 1, v[[MUL_HI]]
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188 ; GCN: buffer_store_dwordx2 v{{\[}}[[MUL_LO]]:[[HI]]{{\]}}
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121
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189 define amdgpu_kernel void @test_umul24_i33(i64 addrspace(1)* %out, i33 %a, i33 %b) {
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120
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190 entry:
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191 %tmp0 = shl i33 %a, 9
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192 %a_24 = lshr i33 %tmp0, 9
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193 %tmp1 = shl i33 %b, 9
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194 %b_24 = lshr i33 %tmp1, 9
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195 %tmp2 = mul i33 %a_24, %b_24
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196 %ext = zext i33 %tmp2 to i64
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197 store i64 %ext, i64 addrspace(1)* %out
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198 ret void
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199 }
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200
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201 ; FUNC-LABEL: {{^}}test_umulhi24_i33:
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202 ; GCN: s_load_dword s
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203 ; GCN: s_load_dword s
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204 ; GCN-NOT: and
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205 ; GCN-NOT: lshr
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206 ; GCN: v_mul_hi_u32_u24_e32 v[[MUL_HI:[0-9]+]],
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207 ; GCN-NEXT: v_and_b32_e32 v[[HI:[0-9]+]], 1, v[[MUL_HI]]
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208 ; GCN-NEXT: buffer_store_dword v[[HI]]
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121
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209 define amdgpu_kernel void @test_umulhi24_i33(i32 addrspace(1)* %out, i33 %a, i33 %b) {
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120
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210 entry:
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211 %tmp0 = shl i33 %a, 9
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212 %a_24 = lshr i33 %tmp0, 9
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213 %tmp1 = shl i33 %b, 9
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214 %b_24 = lshr i33 %tmp1, 9
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215 %tmp2 = mul i33 %a_24, %b_24
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216 %hi = lshr i33 %tmp2, 32
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217 %trunc = trunc i33 %hi to i32
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218 store i32 %trunc, i32 addrspace(1)* %out
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219 ret void
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220 }
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