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annotate test/CodeGen/AMDGPU/predicates.ll @ 128:c347d3398279 default tip

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fix
author mir3636
date Wed, 06 Dec 2017 14:37:17 +0900
parents 803732b1fca8
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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1 ; RUN: llc -spec-exec-max-speculation-cost=0 -march=r600 -r600-ir-structurize=0 -mcpu=redwood < %s | FileCheck %s
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3 ; These tests make sure the compiler is optimizing branches using predicates
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4 ; when it is legal to do so.
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5
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6 ; CHECK-LABEL: {{^}}simple_if:
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7 ; CHECK: PRED_SET{{[EGN][ET]*}}_INT * Pred,
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8 ; CHECK: LSHL * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, Pred_sel
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9 define amdgpu_kernel void @simple_if(i32 addrspace(1)* %out, i32 %in) {
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10 entry:
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11 %cmp0 = icmp sgt i32 %in, 0
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12 br i1 %cmp0, label %IF, label %ENDIF
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13
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14 IF:
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15 %tmp1 = shl i32 %in, 1
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16 br label %ENDIF
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17
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18 ENDIF:
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19 %tmp2 = phi i32 [ %in, %entry ], [ %tmp1, %IF ]
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20 store i32 %tmp2, i32 addrspace(1)* %out
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21 ret void
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22 }
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23
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24 ; CHECK-LABEL: {{^}}simple_if_else:
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25 ; CHECK: PRED_SET{{[EGN][ET]*}}_INT * Pred,
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26 ; CHECK: LSH{{[LR] \* T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, Pred_sel
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27 ; CHECK: LSH{{[LR] \* T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, Pred_sel
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28 define amdgpu_kernel void @simple_if_else(i32 addrspace(1)* %out, i32 %in) {
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29 entry:
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30 %0 = icmp sgt i32 %in, 0
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31 br i1 %0, label %IF, label %ELSE
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32
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33 IF:
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34 %1 = shl i32 %in, 1
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35 br label %ENDIF
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36
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37 ELSE:
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38 %2 = lshr i32 %in, 1
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39 br label %ENDIF
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40
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41 ENDIF:
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42 %3 = phi i32 [ %1, %IF ], [ %2, %ELSE ]
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43 store i32 %3, i32 addrspace(1)* %out
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44 ret void
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45 }
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46
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47 ; CHECK-LABEL: {{^}}nested_if:
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48 ; CHECK: ALU_PUSH_BEFORE
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49 ; CHECK: JUMP
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50 ; CHECK: POP
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51 ; CHECK: PRED_SET{{[EGN][ET]*}}_INT * Exec
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52 ; CHECK: PRED_SET{{[EGN][ET]*}}_INT * Pred,
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53 ; CHECK: LSHL * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, Pred_sel
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54 define amdgpu_kernel void @nested_if(i32 addrspace(1)* %out, i32 %in) {
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55 entry:
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56 %0 = icmp sgt i32 %in, 0
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57 br i1 %0, label %IF0, label %ENDIF
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58
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59 IF0:
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60 %1 = add i32 %in, 10
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61 %2 = icmp sgt i32 %1, 0
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62 br i1 %2, label %IF1, label %ENDIF
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63
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64 IF1:
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65 %3 = shl i32 %1, 1
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66 br label %ENDIF
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67
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68 ENDIF:
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69 %4 = phi i32 [%in, %entry], [%1, %IF0], [%3, %IF1]
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70 store i32 %4, i32 addrspace(1)* %out
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71 ret void
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72 }
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73
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74 ; CHECK-LABEL: {{^}}nested_if_else:
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75 ; CHECK: ALU_PUSH_BEFORE
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76 ; CHECK: JUMP
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77 ; CHECK: POP
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78 ; CHECK: PRED_SET{{[EGN][ET]*}}_INT * Exec
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79 ; CHECK: PRED_SET{{[EGN][ET]*}}_INT * Pred,
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80 ; CHECK: LSH{{[LR] \* T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, Pred_sel
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81 ; CHECK: LSH{{[LR] \* T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, Pred_sel
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82 define amdgpu_kernel void @nested_if_else(i32 addrspace(1)* %out, i32 %in) {
0
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83 entry:
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84 %0 = icmp sgt i32 %in, 0
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85 br i1 %0, label %IF0, label %ENDIF
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86
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87 IF0:
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88 %1 = add i32 %in, 10
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89 %2 = icmp sgt i32 %1, 0
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90 br i1 %2, label %IF1, label %ELSE1
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91
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92 IF1:
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93 %3 = shl i32 %1, 1
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94 br label %ENDIF
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95
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96 ELSE1:
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97 %4 = lshr i32 %in, 1
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98 br label %ENDIF
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99
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100 ENDIF:
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101 %5 = phi i32 [%in, %entry], [%3, %IF1], [%4, %ELSE1]
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102 store i32 %5, i32 addrspace(1)* %out
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103 ret void
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104 }