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121
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1 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri < %s | FileCheck -check-prefix=GCN %s
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120
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2
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3 ; This shows that the amount of LDS estimate is sensitive to the order
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4 ; of the LDS globals.
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5
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6 ; Both of these functions use the same amount of LDS, but the total
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7 ; changes depending on the visit order of first use.
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8
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9 ; The one with the suboptimal order resulting in extra padding exceeds
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10 ; the desired limit
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11
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12 ; The padding estimate heuristic used by the promote alloca pass
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13 ; is mostly determined by the order of the globals,
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14
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15 ; Raw usage = 1060 bytes
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16 ; Rounded usage:
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17 ; 292 + (4 pad) + 256 + (8 pad) + 512 = 1072
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18 ; 512 + (0 pad) + 256 + (0 pad) + 292 = 1060
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19
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20 ; At default occupancy guess of 7, 2340 bytes available total.
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21
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22 ; 1280 need to be left to promote alloca
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23 ; optimally packed, this requires
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24
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25
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26 @lds0 = internal unnamed_addr addrspace(3) global [32 x <4 x i32>] undef, align 16
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27 @lds2 = internal unnamed_addr addrspace(3) global [32 x i64] undef, align 8
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28 @lds1 = internal unnamed_addr addrspace(3) global [73 x i32] undef, align 4
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29
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30
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31 ; GCN-LABEL: {{^}}promote_alloca_size_order_0:
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32 ; GCN: workgroup_group_segment_byte_size = 2340
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121
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33 define amdgpu_kernel void @promote_alloca_size_order_0(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in, i32 %idx) #0 {
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120
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34 entry:
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35 %stack = alloca [5 x i32], align 4
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36 %tmp0 = load i32, i32 addrspace(1)* %in, align 4
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37 %arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %tmp0
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38 store i32 4, i32* %arrayidx1, align 4
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39 %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1
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40 %tmp1 = load i32, i32 addrspace(1)* %arrayidx2, align 4
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41 %arrayidx3 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %tmp1
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42 store i32 5, i32* %arrayidx3, align 4
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43 %arrayidx10 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 0
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44 %tmp2 = load i32, i32* %arrayidx10, align 4
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45 store i32 %tmp2, i32 addrspace(1)* %out, align 4
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46 %arrayidx12 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 1
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47 %tmp3 = load i32, i32* %arrayidx12
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48 %arrayidx13 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1
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49 store i32 %tmp3, i32 addrspace(1)* %arrayidx13
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50
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51 %gep.lds1 = getelementptr inbounds [73 x i32], [73 x i32] addrspace(3)* @lds1, i32 0, i32 %idx
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52 store volatile i32 0, i32 addrspace(3)* %gep.lds1, align 4
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53
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54 %gep.lds2 = getelementptr inbounds [32 x i64], [32 x i64] addrspace(3)* @lds2, i32 0, i32 %idx
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55 store volatile i64 0, i64 addrspace(3)* %gep.lds2, align 8
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56
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57 %gep.lds0 = getelementptr inbounds [32 x <4 x i32>], [32 x <4 x i32>] addrspace(3)* @lds0, i32 0, i32 %idx
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58 store volatile <4 x i32> zeroinitializer, <4 x i32> addrspace(3)* %gep.lds0, align 16
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59
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60 ret void
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61 }
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62
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63 ; GCN-LABEL: {{^}}promote_alloca_size_order_1:
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64 ; GCN: workgroup_group_segment_byte_size = 2352
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121
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65 define amdgpu_kernel void @promote_alloca_size_order_1(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in, i32 %idx) #0 {
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120
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66 entry:
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67 %stack = alloca [5 x i32], align 4
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68 %tmp0 = load i32, i32 addrspace(1)* %in, align 4
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69 %arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %tmp0
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70 store i32 4, i32* %arrayidx1, align 4
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71 %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1
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72 %tmp1 = load i32, i32 addrspace(1)* %arrayidx2, align 4
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73 %arrayidx3 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %tmp1
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74 store i32 5, i32* %arrayidx3, align 4
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75 %arrayidx10 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 0
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76 %tmp2 = load i32, i32* %arrayidx10, align 4
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77 store i32 %tmp2, i32 addrspace(1)* %out, align 4
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78 %arrayidx12 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 1
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79 %tmp3 = load i32, i32* %arrayidx12
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80 %arrayidx13 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1
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81 store i32 %tmp3, i32 addrspace(1)* %arrayidx13
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82
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83 %gep.lds0 = getelementptr inbounds [32 x <4 x i32>], [32 x <4 x i32>] addrspace(3)* @lds0, i32 0, i32 %idx
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84 store volatile <4 x i32> zeroinitializer, <4 x i32> addrspace(3)* %gep.lds0, align 16
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85
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86 %gep.lds2 = getelementptr inbounds [32 x i64], [32 x i64] addrspace(3)* @lds2, i32 0, i32 %idx
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87 store volatile i64 0, i64 addrspace(3)* %gep.lds2, align 8
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88
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89 %gep.lds1 = getelementptr inbounds [73 x i32], [73 x i32] addrspace(3)* @lds1, i32 0, i32 %idx
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90 store volatile i32 0, i32 addrspace(3)* %gep.lds1, align 4
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91
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92 ret void
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93 }
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94
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95 @lds3 = internal unnamed_addr addrspace(3) global [13 x i32] undef, align 4
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96 @lds4 = internal unnamed_addr addrspace(3) global [63 x <4 x i32>] undef, align 16
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97
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98 ; The guess from the alignment padding pushes this over the determined
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99 ; size limit, so it isn't promoted
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100
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101 ; GCN-LABEL: {{^}}promote_alloca_align_pad_guess_over_limit:
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102 ; GCN: workgroup_group_segment_byte_size = 1060
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121
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103 define amdgpu_kernel void @promote_alloca_align_pad_guess_over_limit(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in, i32 %idx) #0 {
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120
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104 entry:
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105 %stack = alloca [5 x i32], align 4
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106 %tmp0 = load i32, i32 addrspace(1)* %in, align 4
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107 %arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %tmp0
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108 store i32 4, i32* %arrayidx1, align 4
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109 %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1
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110 %tmp1 = load i32, i32 addrspace(1)* %arrayidx2, align 4
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111 %arrayidx3 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %tmp1
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112 store i32 5, i32* %arrayidx3, align 4
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113 %arrayidx10 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 0
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114 %tmp2 = load i32, i32* %arrayidx10, align 4
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115 store i32 %tmp2, i32 addrspace(1)* %out, align 4
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116 %arrayidx12 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 1
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117 %tmp3 = load i32, i32* %arrayidx12
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118 %arrayidx13 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1
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119 store i32 %tmp3, i32 addrspace(1)* %arrayidx13
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120
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121 %gep.lds3 = getelementptr inbounds [13 x i32], [13 x i32] addrspace(3)* @lds3, i32 0, i32 %idx
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122 store volatile i32 0, i32 addrspace(3)* %gep.lds3, align 4
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123
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124 %gep.lds4 = getelementptr inbounds [63 x <4 x i32>], [63 x <4 x i32>] addrspace(3)* @lds4, i32 0, i32 %idx
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125 store volatile <4 x i32> zeroinitializer, <4 x i32> addrspace(3)* %gep.lds4, align 16
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126
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127 ret void
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128 }
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129
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130 attributes #0 = { nounwind "amdgpu-flat-work-group-size"="64,64" "amdgpu-waves-per-eu"="1,7" }
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