annotate test/CodeGen/AMDGPU/promote-alloca-volatile.ll @ 128:c347d3398279 default tip

fix
author mir3636
date Wed, 06 Dec 2017 14:37:17 +0900
parents 803732b1fca8
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
120
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
1 ; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -amdgpu-promote-alloca < %s | FileCheck %s
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
2
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
3 ; CHECK-LABEL: @volatile_load(
121
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
4 ; CHECK: alloca [4 x i32]
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
5 ; CHECK: load volatile i32, i32*
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
6 define amdgpu_kernel void @volatile_load(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) {
120
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
7 entry:
121
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
8 %stack = alloca [4 x i32], align 4
120
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
9 %tmp = load i32, i32 addrspace(1)* %in, align 4
121
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
10 %arrayidx1 = getelementptr inbounds [4 x i32], [4 x i32]* %stack, i32 0, i32 %tmp
120
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
11 %load = load volatile i32, i32* %arrayidx1
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
12 store i32 %load, i32 addrspace(1)* %out
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
13 ret void
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
14 }
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
15
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
16 ; CHECK-LABEL: @volatile_store(
121
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
17 ; CHECK: alloca [4 x i32]
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
18 ; CHECK: store volatile i32 %tmp, i32*
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
19 define amdgpu_kernel void @volatile_store(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) {
120
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
20 entry:
121
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
21 %stack = alloca [4 x i32], align 4
120
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
22 %tmp = load i32, i32 addrspace(1)* %in, align 4
121
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
23 %arrayidx1 = getelementptr inbounds [4 x i32], [4 x i32]* %stack, i32 0, i32 %tmp
120
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
24 store volatile i32 %tmp, i32* %arrayidx1
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
25 ret void
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
26 }
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
27
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
28 ; Has on OK non-volatile user but also a volatile user
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
29 ; CHECK-LABEL: @volatile_and_non_volatile_load(
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
30 ; CHECK: alloca double
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
31 ; CHECK: load double
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
32 ; CHECK: load volatile double
121
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
33 define amdgpu_kernel void @volatile_and_non_volatile_load(double addrspace(1)* nocapture %arg, i32 %arg1) #0 {
120
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
34 bb:
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
35 %tmp = alloca double, align 8
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
36 store double 0.000000e+00, double* %tmp, align 8
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
37
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
38 %tmp4 = load double, double* %tmp, align 8
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
39 %tmp5 = load volatile double, double* %tmp, align 8
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
40
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
41 store double %tmp4, double addrspace(1)* %arg
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
42 ret void
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
43 }
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
44
1172e4bd9c6f update 4.0.0
mir3636
parents:
diff changeset
45 attributes #0 = { nounwind }