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1 # RUN: llc -march=amdgcn -misched=converge -run-pass machine-scheduler %s -o - -debug-only=machine-scheduler 2>&1 | FileCheck %s
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2 # REQUIRES: asserts
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3
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4 # Check there is no SReg_32 pressure created by DS_* instructions because of M0 use
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5
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6 # CHECK: ScheduleDAGMILive::schedule starting
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7 # CHECK: SU({{.*}} = DS_READ_B32 {{.*}} %M0<imp-use>, %EXEC<imp-use>
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8 # CHECK: Pressure Diff : {{$}}
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9 # CHECK: SU({{.*}} DS_WRITE_B32
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10
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11 ---
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12 name: mo_pset
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13 alignment: 0
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14 exposesReturnsTwice: false
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15 legalized: false
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16 regBankSelected: false
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17 selected: false
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18 tracksRegLiveness: true
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19 registers:
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20 - { id: 0, class: sreg_128 }
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21 - { id: 1, class: sgpr_64 }
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22 - { id: 2, class: sreg_32_xm0 }
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23 - { id: 3, class: sgpr_32 }
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24 - { id: 4, class: vgpr_32 }
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25 - { id: 5, class: sreg_32_xm0_xexec }
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26 - { id: 6, class: vgpr_32 }
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27 - { id: 7, class: vgpr_32 }
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28 - { id: 8, class: vgpr_32 }
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29 liveins:
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30 - { reg: '%sgpr4_sgpr5', virtual-reg: '%1' }
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31 frameInfo:
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32 isFrameAddressTaken: false
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33 isReturnAddressTaken: false
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34 hasStackMap: false
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35 hasPatchPoint: false
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36 stackSize: 0
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37 offsetAdjustment: 0
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38 maxAlignment: 0
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39 adjustsStack: false
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40 hasCalls: false
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41 maxCallFrameSize: 0
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42 hasOpaqueSPAdjustment: false
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43 hasVAStart: false
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44 hasMustTailInVarArgFunc: false
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45 body: |
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46 bb.0:
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47 liveins: %sgpr4_sgpr5
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48
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49 %1 = COPY %sgpr4_sgpr5
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50 %5 = S_LOAD_DWORD_IMM %1, 0, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(2)* undef`)
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51 %m0 = S_MOV_B32 -1
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52 %7 = COPY %5
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53 %6 = DS_READ_B32 %7, 0, 0, implicit %m0, implicit %exec
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54 DS_WRITE_B32 %7, %6, 4, 0, implicit killed %m0, implicit %exec
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55 S_ENDPGM
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56
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57 ...
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