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121
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1 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -amdgpu-sdwa-peephole=0 -mattr=-fp64-fp16-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=NOSDWA -check-prefix=GCN %s
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2 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -amdgpu-sdwa-peephole -mattr=-fp64-fp16-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=SDWA -check-prefix=GCN %s
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3 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -amdgpu-sdwa-peephole -mattr=-fp64-fp16-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9 -check-prefix=SDWA -check-prefix=GCN %s
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4
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5 ; GCN-LABEL: {{^}}add_shr_i32:
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6 ; NOSDWA: v_lshrrev_b32_e32 v[[DST:[0-9]+]], 16, v{{[0-9]+}}
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7 ; NOSDWA: v_add_i32_e32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v[[DST]]
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8 ; NOSDWA-NOT: v_add_i32_sdwa
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9
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10 ; SDWA: v_add_i32_sdwa v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
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11
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12 define amdgpu_kernel void @add_shr_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
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13 %a = load i32, i32 addrspace(1)* %in, align 4
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14 %shr = lshr i32 %a, 16
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15 %add = add i32 %a, %shr
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16 store i32 %add, i32 addrspace(1)* %out, align 4
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17 ret void
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18 }
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19
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20 ; GCN-LABEL: {{^}}sub_shr_i32:
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21 ; NOSDWA: v_lshrrev_b32_e32 v[[DST:[0-9]+]], 16, v{{[0-9]+}}
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22 ; NOSDWA: v_subrev_i32_e32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v[[DST]]
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23 ; NOSDWA-NOT: v_subrev_i32_sdwa
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24
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25 ; SDWA: v_subrev_i32_sdwa v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
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26
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27 define amdgpu_kernel void @sub_shr_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
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28 %a = load i32, i32 addrspace(1)* %in, align 4
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29 %shr = lshr i32 %a, 16
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30 %sub = sub i32 %shr, %a
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31 store i32 %sub, i32 addrspace(1)* %out, align 4
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32 ret void
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33 }
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34
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35 ; GCN-LABEL: {{^}}mul_shr_i32:
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36 ; NOSDWA: v_lshrrev_b32_e32 v[[DST0:[0-9]+]], 16, v{{[0-9]+}}
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37 ; NOSDWA: v_lshrrev_b32_e32 v[[DST1:[0-9]+]], 16, v{{[0-9]+}}
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38 ; NOSDWA: v_mul_u32_u24_e32 v{{[0-9]+}}, v[[DST0]], v[[DST1]]
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39 ; NOSDWA-NOT: v_mul_u32_u24_sdwa
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40
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41 ; SDWA: v_mul_u32_u24_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
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42
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43 define amdgpu_kernel void @mul_shr_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in1, i32 addrspace(1)* %in2) {
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44 %a = load i32, i32 addrspace(1)* %in1, align 4
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45 %b = load i32, i32 addrspace(1)* %in2, align 4
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46 %shra = lshr i32 %a, 16
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47 %shrb = lshr i32 %b, 16
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48 %mul = mul i32 %shra, %shrb
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49 store i32 %mul, i32 addrspace(1)* %out, align 4
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50 ret void
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51 }
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52
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53 ; GCN-LABEL: {{^}}mul_i16:
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54 ; NOSDWA: v_mul_lo_i32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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55 ; NOSDWA-NOT: v_mul_u32_u24_sdwa
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56 ; SDWA: v_mul_lo_i32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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57 ; SDWA-NOT: v_mul_u32_u24_sdwa
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58
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59 define amdgpu_kernel void @mul_i16(i16 addrspace(1)* %out, i16 addrspace(1)* %ina, i16 addrspace(1)* %inb) {
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60 entry:
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61 %a = load i16, i16 addrspace(1)* %ina, align 4
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62 %b = load i16, i16 addrspace(1)* %inb, align 4
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63 %mul = mul i16 %a, %b
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64 store i16 %mul, i16 addrspace(1)* %out, align 4
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65 ret void
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66 }
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67
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68 ; GCN-LABEL: {{^}}mul_v2i16:
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69 ; NOSDWA: v_lshrrev_b32_e32 v[[DST0:[0-9]+]], 16, v{{[0-9]+}}
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70 ; NOSDWA: v_lshrrev_b32_e32 v[[DST1:[0-9]+]], 16, v{{[0-9]+}}
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71 ; NOSDWA: v_mul_u32_u24_e32 v[[DST_MUL:[0-9]+]], v[[DST0]], v[[DST1]]
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72 ; NOSDWA: v_lshlrev_b32_e32 v[[DST_SHL:[0-9]+]], 16, v[[DST_MUL]]
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73 ; NOSDWA: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v[[DST_SHL]]
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74 ; NOSDWA-NOT: v_mul_u32_u24_sdwa
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75
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76 ; VI-DAG: v_mul_u32_u24_sdwa v[[DST_MUL_LO:[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:WORD_0
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77 ; VI-DAG: v_mul_u32_u24_sdwa v[[DST_MUL_HI:[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
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78 ; VI: v_or_b32_sdwa v{{[0-9]+}}, v[[DST_MUL_LO]], v[[DST_MUL_HI]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
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79
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80 ; GFX9: v_pk_mul_lo_u16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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81
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82 define amdgpu_kernel void @mul_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %ina, <2 x i16> addrspace(1)* %inb) {
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83 entry:
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84 %a = load <2 x i16>, <2 x i16> addrspace(1)* %ina, align 4
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85 %b = load <2 x i16>, <2 x i16> addrspace(1)* %inb, align 4
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86 %mul = mul <2 x i16> %a, %b
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87 store <2 x i16> %mul, <2 x i16> addrspace(1)* %out, align 4
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88 ret void
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89 }
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90
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91 ; GCN-LABEL: {{^}}mul_v4i16:
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92 ; NOSDWA: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v{{[0-9]+}}
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93 ; NOSDWA: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v{{[0-9]+}}
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94 ; NOSDWA: v_mul_u32_u24_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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95 ; NOSDWA: v_lshlrev_b32_e32 v{{[0-9]+}}, 16, v{{[0-9]+}}
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96 ; NOSDWA: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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97 ; NOSDWA-NOT: v_mul_u32_u24_sdwa
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98
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99 ; VI-DAG: v_mul_u32_u24_sdwa v[[DST_MUL0:[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:WORD_0
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100 ; VI-DAG: v_mul_u32_u24_sdwa v[[DST_MUL1:[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
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101 ; VI-DAG: v_mul_u32_u24_sdwa v[[DST_MUL2:[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:WORD_0
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102 ; VI-DAG: v_mul_u32_u24_sdwa v[[DST_MUL3:[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
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103 ; VI-DAG: v_or_b32_sdwa v{{[0-9]+}}, v[[DST_MUL2]], v[[DST_MUL3]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
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104 ; VI-DAG: v_or_b32_sdwa v{{[0-9]+}}, v[[DST_MUL0]], v[[DST_MUL1]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
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105
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106 ; GFX9-DAG: v_pk_mul_lo_u16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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107 ; GFX9-DAG: v_pk_mul_lo_u16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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108
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109 define amdgpu_kernel void @mul_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> addrspace(1)* %ina, <4 x i16> addrspace(1)* %inb) {
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110 entry:
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111 %a = load <4 x i16>, <4 x i16> addrspace(1)* %ina, align 4
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112 %b = load <4 x i16>, <4 x i16> addrspace(1)* %inb, align 4
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113 %mul = mul <4 x i16> %a, %b
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114 store <4 x i16> %mul, <4 x i16> addrspace(1)* %out, align 4
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115 ret void
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116 }
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117
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118 ; GCN-LABEL: {{^}}mul_v8i16:
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119 ; NOSDWA: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v{{[0-9]+}}
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120 ; NOSDWA: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v{{[0-9]+}}
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121 ; NOSDWA: v_mul_u32_u24_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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122 ; NOSDWA: v_lshlrev_b32_e32 v{{[0-9]+}}, 16, v{{[0-9]+}}
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123 ; NOSDWA: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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124 ; NOSDWA-NOT: v_mul_u32_u24_sdwa
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125
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126 ; VI-DAG: v_mul_u32_u24_sdwa v[[DST_MUL0:[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:WORD_0
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127 ; VI-DAG: v_mul_u32_u24_sdwa v[[DST_MUL1:[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
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128 ; VI-DAG: v_mul_u32_u24_sdwa v[[DST_MUL2:[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:WORD_0
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129 ; VI-DAG: v_mul_u32_u24_sdwa v[[DST_MUL3:[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
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130 ; VI-DAG: v_mul_u32_u24_sdwa v[[DST_MUL4:[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:WORD_0
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131 ; VI-DAG: v_mul_u32_u24_sdwa v[[DST_MUL5:[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
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132 ; VI-DAG: v_mul_u32_u24_sdwa v[[DST_MUL6:[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:WORD_0
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133 ; VI-DAG: v_mul_u32_u24_sdwa v[[DST_MUL7:[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
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134 ; VI-DAG: v_or_b32_sdwa v{{[0-9]+}}, v[[DST_MUL6]], v[[DST_MUL7]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
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135 ; VI-DAG: v_or_b32_sdwa v{{[0-9]+}}, v[[DST_MUL4]], v[[DST_MUL5]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
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136 ; VI-DAG: v_or_b32_sdwa v{{[0-9]+}}, v[[DST_MUL2]], v[[DST_MUL3]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
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137 ; VI-DAG: v_or_b32_sdwa v{{[0-9]+}}, v[[DST_MUL0]], v[[DST_MUL1]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
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138
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139 ; GFX9-DAG: v_pk_mul_lo_u16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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140 ; GFX9-DAG: v_pk_mul_lo_u16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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141 ; GFX9-DAG: v_pk_mul_lo_u16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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142 ; GFX9-DAG: v_pk_mul_lo_u16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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143
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144 define amdgpu_kernel void @mul_v8i16(<8 x i16> addrspace(1)* %out, <8 x i16> addrspace(1)* %ina, <8 x i16> addrspace(1)* %inb) {
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145 entry:
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146 %a = load <8 x i16>, <8 x i16> addrspace(1)* %ina, align 4
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147 %b = load <8 x i16>, <8 x i16> addrspace(1)* %inb, align 4
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148 %mul = mul <8 x i16> %a, %b
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149 store <8 x i16> %mul, <8 x i16> addrspace(1)* %out, align 4
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150 ret void
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151 }
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152
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153 ; GCN-LABEL: {{^}}mul_half:
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154 ; NOSDWA: v_mul_f16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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155 ; NOSDWA-NOT: v_mul_f16_sdwa
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156 ; SDWA: v_mul_f16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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157 ; SDWA-NOT: v_mul_f16_sdwa
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158
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159 define amdgpu_kernel void @mul_half(half addrspace(1)* %out, half addrspace(1)* %ina, half addrspace(1)* %inb) {
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160 entry:
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161 %a = load half, half addrspace(1)* %ina, align 4
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162 %b = load half, half addrspace(1)* %inb, align 4
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163 %mul = fmul half %a, %b
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164 store half %mul, half addrspace(1)* %out, align 4
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165 ret void
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166 }
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167
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168 ; GCN-LABEL: {{^}}mul_v2half:
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169 ; NOSDWA: v_lshrrev_b32_e32 v[[DST0:[0-9]+]], 16, v{{[0-9]+}}
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170 ; NOSDWA: v_lshrrev_b32_e32 v[[DST1:[0-9]+]], 16, v{{[0-9]+}}
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171 ; NOSDWA: v_mul_f16_e32 v[[DST_MUL:[0-9]+]], v[[DST0]], v[[DST1]]
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172 ; NOSDWA: v_lshlrev_b32_e32 v[[DST_SHL:[0-9]+]], 16, v[[DST_MUL]]
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173 ; NOSDWA: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v[[DST_SHL]]
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174 ; NOSDWA-NOT: v_mul_f16_sdwa
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175
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176 ; VI-DAG: v_mul_f16_sdwa v[[DST_MUL_HI:[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
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177 ; VI-DAG: v_mul_f16_e32 v[[DST_MUL_LO:[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}}
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178 ; VI: v_or_b32_e32 v{{[0-9]+}}, v[[DST_MUL_LO]], v[[DST_MUL_HI]]
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179
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180 ; GFX9: v_pk_mul_f16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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181
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182 define amdgpu_kernel void @mul_v2half(<2 x half> addrspace(1)* %out, <2 x half> addrspace(1)* %ina, <2 x half> addrspace(1)* %inb) {
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183 entry:
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184 %a = load <2 x half>, <2 x half> addrspace(1)* %ina, align 4
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185 %b = load <2 x half>, <2 x half> addrspace(1)* %inb, align 4
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186 %mul = fmul <2 x half> %a, %b
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187 store <2 x half> %mul, <2 x half> addrspace(1)* %out, align 4
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188 ret void
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189 }
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190
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191 ; GCN-LABEL: {{^}}mul_v4half:
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192 ; NOSDWA: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v{{[0-9]+}}
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193 ; NOSDWA: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v{{[0-9]+}}
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194 ; NOSDWA: v_mul_f16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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195 ; NOSDWA: v_lshlrev_b32_e32 v{{[0-9]+}}, 16, v{{[0-9]+}}
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196 ; NOSDWA: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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197 ; NOSDWA-NOT: v_mul_f16_sdwa
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198
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199 ; VI-DAG: v_mul_f16_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
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200 ; VI-DAG: v_mul_f16_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
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201 ; VI-DAG: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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202 ; VI-DAG: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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203
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204 ; GFX9-DAG: v_pk_mul_f16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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205 ; GFX9-DAG: v_pk_mul_f16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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206
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|
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207 define amdgpu_kernel void @mul_v4half(<4 x half> addrspace(1)* %out, <4 x half> addrspace(1)* %ina, <4 x half> addrspace(1)* %inb) {
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208 entry:
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209 %a = load <4 x half>, <4 x half> addrspace(1)* %ina, align 4
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210 %b = load <4 x half>, <4 x half> addrspace(1)* %inb, align 4
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211 %mul = fmul <4 x half> %a, %b
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|
212 store <4 x half> %mul, <4 x half> addrspace(1)* %out, align 4
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|
|
213 ret void
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|
|
214 }
|
|
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215
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216 ; GCN-LABEL: {{^}}mul_v8half:
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217 ; NOSDWA: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v{{[0-9]+}}
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218 ; NOSDWA: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v{{[0-9]+}}
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219 ; NOSDWA: v_mul_f16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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220 ; NOSDWA: v_lshlrev_b32_e32 v{{[0-9]+}}, 16, v{{[0-9]+}}
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221 ; NOSDWA: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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222 ; NOSDWA-NOT: v_mul_f16_sdwa
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223
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224 ; VI-DAG: v_mul_f16_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
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225 ; VI-DAG: v_mul_f16_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
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226 ; VI-DAG: v_mul_f16_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
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227 ; VI-DAG: v_mul_f16_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
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228 ; VI-DAG: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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229 ; VI-DAG: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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230 ; VI-DAG: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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231 ; VI-DAG: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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232
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233 ; GFX9-DAG: v_pk_mul_f16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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234 ; GFX9-DAG: v_pk_mul_f16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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235 ; GFX9-DAG: v_pk_mul_f16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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236 ; GFX9-DAG: v_pk_mul_f16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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237
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238 define amdgpu_kernel void @mul_v8half(<8 x half> addrspace(1)* %out, <8 x half> addrspace(1)* %ina, <8 x half> addrspace(1)* %inb) {
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239 entry:
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240 %a = load <8 x half>, <8 x half> addrspace(1)* %ina, align 4
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241 %b = load <8 x half>, <8 x half> addrspace(1)* %inb, align 4
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242 %mul = fmul <8 x half> %a, %b
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243 store <8 x half> %mul, <8 x half> addrspace(1)* %out, align 4
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244 ret void
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245 }
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246
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247 ; GCN-LABEL: {{^}}mul_i8:
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248 ; NOSDWA: v_mul_lo_i32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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249 ; NOSDWA-NOT: v_mul_u32_u24_sdwa
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250 ; SDWA: v_mul_lo_i32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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251 ; SDWA-NOT: v_mul_u32_u24_sdwa
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252
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253 define amdgpu_kernel void @mul_i8(i8 addrspace(1)* %out, i8 addrspace(1)* %ina, i8 addrspace(1)* %inb) {
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254 entry:
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|
255 %a = load i8, i8 addrspace(1)* %ina, align 4
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256 %b = load i8, i8 addrspace(1)* %inb, align 4
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257 %mul = mul i8 %a, %b
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258 store i8 %mul, i8 addrspace(1)* %out, align 4
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259 ret void
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|
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260 }
|
|
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261
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262 ; GCN-LABEL: {{^}}mul_v2i8:
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263 ; NOSDWA: v_lshrrev_b16_e32 v{{[0-9]+}}, 8, v{{[0-9]+}}
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264 ; NOSDWA: v_lshrrev_b16_e32 v{{[0-9]+}}, 8, v{{[0-9]+}}
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265 ; NOSDWA: v_mul_u32_u24_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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266 ; NOSDWA: v_lshlrev_b16_e32 v{{[0-9]+}}, 8, v{{[0-9]+}}
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267 ; NOSDWA: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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268 ; NOSDWA-NOT: v_mul_u32_u24_sdwa
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269
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270 ; VI: v_mul_u32_u24_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:BYTE_1
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271
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272 ; GFX9-DAG: v_mul_lo_u16_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:BYTE_1
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273 ; GFX9-DAG: v_mul_lo_u16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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274 ; GFX9: v_or_b32_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
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275
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276 define amdgpu_kernel void @mul_v2i8(<2 x i8> addrspace(1)* %out, <2 x i8> addrspace(1)* %ina, <2 x i8> addrspace(1)* %inb) {
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|
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277 entry:
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|
|
278 %a = load <2 x i8>, <2 x i8> addrspace(1)* %ina, align 4
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|
|
279 %b = load <2 x i8>, <2 x i8> addrspace(1)* %inb, align 4
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280 %mul = mul <2 x i8> %a, %b
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|
|
281 store <2 x i8> %mul, <2 x i8> addrspace(1)* %out, align 4
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|
|
282 ret void
|
|
|
283 }
|
|
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284
|
|
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285 ; GCN-LABEL: {{^}}mul_v4i8:
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286 ; NOSDWA: v_lshrrev_b16_e32 v{{[0-9]+}}, 8, v{{[0-9]+}}
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287 ; NOSDWA: v_lshrrev_b16_e32 v{{[0-9]+}}, 8, v{{[0-9]+}}
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288 ; NOSDWA: v_mul_u32_u24_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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289 ; NOSDWA: v_lshlrev_b16_e32 v{{[0-9]+}}, 8, v{{[0-9]+}}
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290 ; NOSDWA: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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291 ; NOSDWA-NOT: v_mul_u32_u24_sdwa
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292
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293 ; VI-DAG: v_mul_u32_u24_sdwa
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294 ; VI-DAG: v_mul_u32_u24_sdwa
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295 ; VI-DAG: v_mul_u32_u24_sdwa
|
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296
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297 ; GFX9-DAG: v_mul_lo_u16_sdwa
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298 ; GFX9-DAG: v_mul_lo_u16_sdwa
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299 ; GFX9-DAG: v_mul_lo_u16_sdwa
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300
|
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301 define amdgpu_kernel void @mul_v4i8(<4 x i8> addrspace(1)* %out, <4 x i8> addrspace(1)* %ina, <4 x i8> addrspace(1)* %inb) {
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302 entry:
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|
|
303 %a = load <4 x i8>, <4 x i8> addrspace(1)* %ina, align 4
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|
304 %b = load <4 x i8>, <4 x i8> addrspace(1)* %inb, align 4
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305 %mul = mul <4 x i8> %a, %b
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|
|
306 store <4 x i8> %mul, <4 x i8> addrspace(1)* %out, align 4
|
|
|
307 ret void
|
|
|
308 }
|
|
|
309
|
|
|
310 ; GCN-LABEL: {{^}}mul_v8i8:
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311 ; NOSDWA: v_lshrrev_b16_e32 v{{[0-9]+}}, 8, v{{[0-9]+}}
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312 ; NOSDWA: v_lshrrev_b16_e32 v{{[0-9]+}}, 8, v{{[0-9]+}}
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313 ; NOSDWA: v_mul_u32_u24_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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314 ; NOSDWA: v_lshlrev_b16_e32 v{{[0-9]+}}, 8, v{{[0-9]+}}
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|
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315 ; NOSDWA: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
|
|
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316 ; NOSDWA-NOT: v_mul_u32_u24_sdwa
|
|
|
317
|
|
|
318 ; VI-DAG: v_mul_u32_u24_sdwa
|
|
|
319 ; VI-DAG: v_mul_u32_u24_sdwa
|
|
|
320 ; VI-DAG: v_mul_u32_u24_sdwa
|
|
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321 ; VI-DAG: v_mul_u32_u24_sdwa
|
|
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322 ; VI-DAG: v_mul_u32_u24_sdwa
|
|
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323 ; VI-DAG: v_mul_u32_u24_sdwa
|
|
|
324
|
|
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325 ; GFX9-DAG: v_mul_lo_u16_sdwa
|
|
|
326 ; GFX9-DAG: v_mul_lo_u16_sdwa
|
|
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327 ; GFX9-DAG: v_mul_lo_u16_sdwa
|
|
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328 ; GFX9-DAG: v_mul_lo_u16_sdwa
|
|
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329 ; GFX9-DAG: v_mul_lo_u16_sdwa
|
|
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330 ; GFX9-DAG: v_mul_lo_u16_sdwa
|
|
|
331
|
|
|
332 define amdgpu_kernel void @mul_v8i8(<8 x i8> addrspace(1)* %out, <8 x i8> addrspace(1)* %ina, <8 x i8> addrspace(1)* %inb) {
|
|
|
333 entry:
|
|
|
334 %a = load <8 x i8>, <8 x i8> addrspace(1)* %ina, align 4
|
|
|
335 %b = load <8 x i8>, <8 x i8> addrspace(1)* %inb, align 4
|
|
|
336 %mul = mul <8 x i8> %a, %b
|
|
|
337 store <8 x i8> %mul, <8 x i8> addrspace(1)* %out, align 4
|
|
|
338 ret void
|
|
|
339 }
|
|
|
340
|
|
|
341 ; GCN-LABEL: {{^}}sitofp_v2i16_to_v2f16:
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|
|
342 ; NOSDWA-DAG: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 16
|
|
|
343 ; NOSDWA-DAG: v_ashrrev_i32_e32 v{{[0-9]+}}, 16, v{{[0-9]+}}
|
|
|
344 ; NOSDWA-DAG: v_cvt_f32_i32_e32 v{{[0-9]+}}, v{{[0-9]+}}
|
|
|
345 ; NOSDWA-DAG: v_cvt_f32_i32_e32 v{{[0-9]+}}, v{{[0-9]+}}
|
|
|
346 ; NOSDWA-NOT: v_cvt_f32_i32_sdwa
|
|
|
347
|
|
|
348 ; SDWA-DAG: v_cvt_f32_i32_sdwa v{{[0-9]+}}, sext(v{{[0-9]+}}) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
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|
|
349 ; SDWA-DAG: v_cvt_f32_i32_sdwa v{{[0-9]+}}, sext(v{{[0-9]+}}) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
|
|
|
350
|
|
|
351 define amdgpu_kernel void @sitofp_v2i16_to_v2f16(
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|
|
352 <2 x half> addrspace(1)* %r,
|
|
|
353 <2 x i16> addrspace(1)* %a) {
|
|
|
354 entry:
|
|
|
355 %a.val = load <2 x i16>, <2 x i16> addrspace(1)* %a
|
|
|
356 %r.val = sitofp <2 x i16> %a.val to <2 x half>
|
|
|
357 store <2 x half> %r.val, <2 x half> addrspace(1)* %r
|
|
|
358 ret void
|
|
|
359 }
|
|
|
360
|
|
|
361
|
|
|
362 ; GCN-LABEL: {{^}}mac_v2half:
|
|
|
363 ; NOSDWA: v_lshrrev_b32_e32 v[[DST0:[0-9]+]], 16, v{{[0-9]+}}
|
|
|
364 ; NOSDWA: v_lshrrev_b32_e32 v[[DST1:[0-9]+]], 16, v{{[0-9]+}}
|
|
|
365 ; NOSDWA: v_mac_f16_e32 v[[DST_MAC:[0-9]+]], v[[DST0]], v[[DST1]]
|
|
|
366 ; NOSDWA: v_lshlrev_b32_e32 v[[DST_SHL:[0-9]+]], 16, v[[DST_MAC]]
|
|
|
367 ; NOSDWA: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v[[DST_SHL]]
|
|
|
368 ; NOSDWA-NOT: v_mac_f16_sdwa
|
|
|
369
|
|
|
370 ; VI: v_mac_f16_sdwa v[[DST_MAC:[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
|
|
|
371 ; VI: v_lshlrev_b32_e32 v[[DST_SHL:[0-9]+]], 16, v[[DST_MAC]]
|
|
|
372
|
|
|
373 ; GFX9: v_pk_mul_f16 v[[DST_MUL:[0-9]+]], v{{[0-9]+}}, v[[SRC:[0-9]+]]
|
|
|
374 ; GFX9: v_pk_add_f16 v{{[0-9]+}}, v[[DST_MUL]], v[[SRC]]
|
|
|
375
|
|
|
376 define amdgpu_kernel void @mac_v2half(<2 x half> addrspace(1)* %out, <2 x half> addrspace(1)* %ina, <2 x half> addrspace(1)* %inb) {
|
|
|
377 entry:
|
|
|
378 %a = load <2 x half>, <2 x half> addrspace(1)* %ina, align 4
|
|
|
379 %b = load <2 x half>, <2 x half> addrspace(1)* %inb, align 4
|
|
|
380 %mul = fmul <2 x half> %a, %b
|
|
|
381 %mac = fadd <2 x half> %mul, %b
|
|
|
382 store <2 x half> %mac, <2 x half> addrspace(1)* %out, align 4
|
|
|
383 ret void
|
|
|
384 }
|
|
|
385
|
|
|
386 ; GCN-LABEL: {{^}}immediate_mul_v2i16:
|
|
|
387 ; NOSDWA-NOT: v_mul_u32_u24_sdwa
|
|
|
388 ; VI-DAG: v_mov_b32_e32 v[[M321:[0-9]+]], 0x141
|
|
|
389 ; VI-DAG: v_mov_b32_e32 v[[M123:[0-9]+]], 0x7b
|
|
|
390 ; VI-DAG: v_mul_u32_u24_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v[[M123]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
|
391 ; VI-DAG: v_mul_u32_u24_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v[[M321]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
|
392
|
|
|
393 ; GFX9: s_mov_b32 s[[IMM:[0-9]+]], 0x141007b
|
|
|
394 ; GFX9: v_pk_mul_lo_u16 v{{[0-9]+}}, v{{[0-9]+}}, s[[IMM]]
|
|
|
395
|
|
|
396 define amdgpu_kernel void @immediate_mul_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) {
|
|
|
397 entry:
|
|
|
398 %a = load <2 x i16>, <2 x i16> addrspace(1)* %in, align 4
|
|
|
399 %mul = mul <2 x i16> %a, <i16 123, i16 321>
|
|
|
400 store <2 x i16> %mul, <2 x i16> addrspace(1)* %out, align 4
|
|
|
401 ret void
|
|
|
402 }
|
|
|
403
|
|
|
404 ; Double use of same src - should not convert it
|
|
|
405 ; GCN-LABEL: {{^}}mulmul_v2i16:
|
|
|
406 ; NOSDWA: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v{{[0-9]+}}
|
|
|
407 ; NOSDWA: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v{{[0-9]+}}
|
|
|
408 ; NOSDWA: v_mul_u32_u24_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
|
|
|
409 ; NOSDWA: v_lshlrev_b32_e32 v{{[0-9]+}}, 16, v{{[0-9]+}}
|
|
|
410 ; NOSDWA: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
|
|
|
411 ; NOSDWA-NOT: v_mul_u32_u24_sdwa
|
|
|
412
|
|
|
413 ; VI: v_mul_u32_u24_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
|
414
|
|
|
415 ; GFX9: v_pk_mul_lo_u16 v[[DST1:[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}}
|
|
|
416 ; GFX9: v_pk_mul_lo_u16 v{{[0-9]+}}, v[[DST1]], v{{[0-9]+}}
|
|
|
417
|
|
|
418 define amdgpu_kernel void @mulmul_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %ina, <2 x i16> addrspace(1)* %inb) {
|
|
|
419 entry:
|
|
|
420 %a = load <2 x i16>, <2 x i16> addrspace(1)* %ina, align 4
|
|
|
421 %b = load <2 x i16>, <2 x i16> addrspace(1)* %inb, align 4
|
|
|
422 %mul = mul <2 x i16> %a, %b
|
|
|
423 %mul2 = mul <2 x i16> %mul, %b
|
|
|
424 store <2 x i16> %mul2, <2 x i16> addrspace(1)* %out, align 4
|
|
|
425 ret void
|
|
|
426 }
|
|
|
427
|
|
|
428 ; GCN-LABEL: {{^}}add_bb_v2i16:
|
|
|
429 ; NOSDWA-NOT: v_add_i32_sdwa
|
|
|
430
|
|
|
431 ; VI: v_add_i32_sdwa v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
|
|
|
432
|
|
|
433 ; GFX9: v_pk_add_u16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
|
|
|
434
|
|
|
435 define amdgpu_kernel void @add_bb_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %ina, <2 x i16> addrspace(1)* %inb) {
|
|
|
436 entry:
|
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437 %a = load <2 x i16>, <2 x i16> addrspace(1)* %ina, align 4
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438 %b = load <2 x i16>, <2 x i16> addrspace(1)* %inb, align 4
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439 br label %add_label
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440 add_label:
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441 %add = add <2 x i16> %a, %b
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442 br label %store_label
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443 store_label:
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444 store <2 x i16> %add, <2 x i16> addrspace(1)* %out, align 4
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445 ret void
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446 }
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447
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448
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449 ; Check that "pulling out" SDWA operands works correctly.
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450 ; GCN-LABEL: {{^}}pulled_out_test:
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451 ; NOSDWA-DAG: v_and_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
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452 ; NOSDWA-DAG: v_lshlrev_b16_e32 v{{[0-9]+}}, 8, v{{[0-9]+}}
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453 ; NOSDWA-DAG: v_and_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
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454 ; NOSDWA-DAG: v_lshlrev_b16_e32 v{{[0-9]+}}, 8, v{{[0-9]+}}
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455 ; NOSDWA: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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456 ; NOSDWA-NOT: v_and_b32_sdwa
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457 ; NOSDWA-NOT: v_or_b32_sdwa
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458
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459 ; VI-DAG: v_and_b32_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
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460 ; GFX9-DAG: v_and_b32_sdwa v{{[0-9]+}}, v{{[0-9]+}}, s{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
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461 ; SDWA-DAG: v_lshlrev_b16_e32 v{{[0-9]+}}, 8, v{{[0-9]+}}
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462 ; VI-DAG: v_and_b32_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
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463 ; GFX9-DAG: v_and_b32_sdwa v{{[0-9]+}}, v{{[0-9]+}}, s{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
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464 ; SDWA-DAG: v_lshlrev_b16_e32 v{{[0-9]+}}, 8, v{{[0-9]+}}
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465 ; SDWA: v_or_b32_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
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466
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467 define amdgpu_kernel void @pulled_out_test(<8 x i8> addrspace(1)* %sourceA, <8 x i8> addrspace(1)* %destValues) {
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468 entry:
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469 %idxprom = ashr exact i64 15, 32
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470 %arrayidx = getelementptr inbounds <8 x i8>, <8 x i8> addrspace(1)* %sourceA, i64 %idxprom
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471 %tmp = load <8 x i8>, <8 x i8> addrspace(1)* %arrayidx, align 8
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472
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473 %tmp1 = extractelement <8 x i8> %tmp, i32 0
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474 %tmp2 = extractelement <8 x i8> %tmp, i32 1
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475 %tmp3 = extractelement <8 x i8> %tmp, i32 2
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476 %tmp4 = extractelement <8 x i8> %tmp, i32 3
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477 %tmp5 = extractelement <8 x i8> %tmp, i32 4
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478 %tmp6 = extractelement <8 x i8> %tmp, i32 5
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479 %tmp7 = extractelement <8 x i8> %tmp, i32 6
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480 %tmp8 = extractelement <8 x i8> %tmp, i32 7
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481
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482 %tmp9 = insertelement <2 x i8> undef, i8 %tmp1, i32 0
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483 %tmp10 = insertelement <2 x i8> %tmp9, i8 %tmp2, i32 1
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484 %tmp11 = insertelement <2 x i8> undef, i8 %tmp3, i32 0
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485 %tmp12 = insertelement <2 x i8> %tmp11, i8 %tmp4, i32 1
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486 %tmp13 = insertelement <2 x i8> undef, i8 %tmp5, i32 0
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487 %tmp14 = insertelement <2 x i8> %tmp13, i8 %tmp6, i32 1
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488 %tmp15 = insertelement <2 x i8> undef, i8 %tmp7, i32 0
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489 %tmp16 = insertelement <2 x i8> %tmp15, i8 %tmp8, i32 1
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490
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491 %tmp17 = shufflevector <2 x i8> %tmp10, <2 x i8> %tmp12, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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492 %tmp18 = shufflevector <2 x i8> %tmp14, <2 x i8> %tmp16, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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493 %tmp19 = shufflevector <4 x i8> %tmp17, <4 x i8> %tmp18, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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494
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495 %arrayidx5 = getelementptr inbounds <8 x i8>, <8 x i8> addrspace(1)* %destValues, i64 %idxprom
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496 store <8 x i8> %tmp19, <8 x i8> addrspace(1)* %arrayidx5, align 8
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497 ret void
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498 }
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