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annotate test/CodeGen/AMDGPU/shl.v2i16.ll @ 128:c347d3398279 default tip

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fix
author mir3636
date Wed, 06 Dec 2017 14:37:17 +0900
parents 803732b1fca8
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
121
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1 ; RUN: llc -march=amdgcn -mcpu=gfx901 -mattr=-flat-for-global -verify-machineinstrs -enable-packed-inlinable-literals < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s
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2 ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=CIVI %s
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3 ; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=CIVI %s
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4
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5 ; GCN-LABEL: {{^}}s_shl_v2i16:
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6 ; GFX9: s_load_dword [[LHS:s[0-9]+]]
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7 ; GFX9: s_load_dword [[RHS:s[0-9]+]]
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8 ; GFX9: v_mov_b32_e32 [[VLHS:v[0-9]+]], [[LHS]]
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9 ; GFX9: v_pk_lshlrev_b16 [[RESULT:v[0-9]+]], [[RHS]], [[VLHS]]
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10
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11 ; VI: v_lshlrev_b32_e32
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12 ; VI: v_lshlrev_b32_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
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13 ; VI: v_or_b32_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
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14
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15 ; CI-DAG: v_lshlrev_b32_e32
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16 ; CI-DAG: v_and_b32_e32 v{{[0-9]+}}, 0xffff, v{{[0-9]+}}
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17 ; CI-DAG: v_lshlrev_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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18 ; CI-DAG: v_lshlrev_b32_e32 v{{[0-9]+}}, 16, v{{[0-9]+}}
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19 ; CI: v_or_b32_e32
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20 define amdgpu_kernel void @s_shl_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> %lhs, <2 x i16> %rhs) #0 {
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21 %result = shl <2 x i16> %lhs, %rhs
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22 store <2 x i16> %result, <2 x i16> addrspace(1)* %out
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23 ret void
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24 }
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25
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26 ; GCN-LABEL: {{^}}v_shl_v2i16:
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27 ; GCN: {{buffer|flat|global}}_load_dword [[LHS:v[0-9]+]]
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28 ; GCN: {{buffer|flat|global}}_load_dword [[RHS:v[0-9]+]]
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29 ; GFX9: v_pk_lshlrev_b16 [[RESULT:v[0-9]+]], [[RHS]], [[LHS]]
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30
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31 ; VI: v_lshlrev_b16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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32 ; VI: v_lshlrev_b16_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
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33 ; VI: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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34
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35 ; CI: s_mov_b32 [[MASK:s[0-9]+]], 0xffff{{$}}
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36 ; CI: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, [[LHS]]
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37 ; CI: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v{{[0-9]+}}
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38 ; CI: v_lshlrev_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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39 ; CI: v_lshl_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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40 ; CI: v_lshlrev_b32_e32 v{{[0-9]+}}, 16, v{{[0-9]+}}
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41 ; CI: v_and_b32_e32 v{{[0-9]+}}, [[MASK]], v{{[0-9]+}}
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42 ; CI: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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43 define amdgpu_kernel void @v_shl_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 {
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44 %tid = call i32 @llvm.amdgcn.workitem.id.x()
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45 %tid.ext = sext i32 %tid to i64
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46 %in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext
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47 %out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext
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48 %b_ptr = getelementptr <2 x i16>, <2 x i16> addrspace(1)* %in.gep, i32 1
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49 %a = load <2 x i16>, <2 x i16> addrspace(1)* %in.gep
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50 %b = load <2 x i16>, <2 x i16> addrspace(1)* %b_ptr
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51 %result = shl <2 x i16> %a, %b
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52 store <2 x i16> %result, <2 x i16> addrspace(1)* %out.gep
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53 ret void
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54 }
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55
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56 ; GCN-LABEL: {{^}}shl_v_s_v2i16:
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57 ; GFX9: s_load_dword [[RHS:s[0-9]+]]
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58 ; GFX9: {{buffer|flat|global}}_load_dword [[LHS:v[0-9]+]]
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59 ; GFX9: v_pk_lshlrev_b16 [[RESULT:v[0-9]+]], [[RHS]], [[LHS]]
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60 define amdgpu_kernel void @shl_v_s_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in, <2 x i16> %sgpr) #0 {
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61 %tid = call i32 @llvm.amdgcn.workitem.id.x()
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62 %tid.ext = sext i32 %tid to i64
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63 %in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext
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64 %out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext
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65 %vgpr = load <2 x i16>, <2 x i16> addrspace(1)* %in.gep
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66 %result = shl <2 x i16> %vgpr, %sgpr
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67 store <2 x i16> %result, <2 x i16> addrspace(1)* %out.gep
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68 ret void
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69 }
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70
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71 ; GCN-LABEL: {{^}}shl_s_v_v2i16:
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72 ; GFX9: s_load_dword [[LHS:s[0-9]+]]
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73 ; GFX9: {{buffer|flat|global}}_load_dword [[RHS:v[0-9]+]]
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74 ; GFX9: v_pk_lshlrev_b16 [[RESULT:v[0-9]+]], [[RHS]], [[LHS]]
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75 define amdgpu_kernel void @shl_s_v_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in, <2 x i16> %sgpr) #0 {
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76 %tid = call i32 @llvm.amdgcn.workitem.id.x()
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77 %tid.ext = sext i32 %tid to i64
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78 %in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext
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79 %out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext
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80 %vgpr = load <2 x i16>, <2 x i16> addrspace(1)* %in.gep
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81 %result = shl <2 x i16> %sgpr, %vgpr
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82 store <2 x i16> %result, <2 x i16> addrspace(1)* %out.gep
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83 ret void
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84 }
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85
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86 ; GCN-LABEL: {{^}}shl_imm_v_v2i16:
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87 ; GCN: {{buffer|flat|global}}_load_dword [[RHS:v[0-9]+]]
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88 ; GFX9: v_pk_lshlrev_b16 [[RESULT:v[0-9]+]], [[RHS]], 8
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89 define amdgpu_kernel void @shl_imm_v_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 {
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90 %tid = call i32 @llvm.amdgcn.workitem.id.x()
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91 %tid.ext = sext i32 %tid to i64
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92 %in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext
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93 %out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext
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94 %vgpr = load <2 x i16>, <2 x i16> addrspace(1)* %in.gep
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95 %result = shl <2 x i16> <i16 8, i16 8>, %vgpr
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96 store <2 x i16> %result, <2 x i16> addrspace(1)* %out.gep
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97 ret void
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98 }
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99
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100 ; GCN-LABEL: {{^}}shl_v_imm_v2i16:
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101 ; GCN: {{buffer|flat|global}}_load_dword [[LHS:v[0-9]+]]
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102 ; GFX9: v_pk_lshlrev_b16 [[RESULT:v[0-9]+]], 8, [[LHS]]
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103 define amdgpu_kernel void @shl_v_imm_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 {
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104 %tid = call i32 @llvm.amdgcn.workitem.id.x()
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105 %tid.ext = sext i32 %tid to i64
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106 %in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext
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107 %out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext
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108 %vgpr = load <2 x i16>, <2 x i16> addrspace(1)* %in.gep
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109 %result = shl <2 x i16> %vgpr, <i16 8, i16 8>
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110 store <2 x i16> %result, <2 x i16> addrspace(1)* %out.gep
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111 ret void
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112 }
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113
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114 ; GCN-LABEL: {{^}}v_shl_v4i16:
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115 ; GCN: {{buffer|flat|global}}_load_dwordx2
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116 ; GCN: {{buffer|flat|global}}_load_dwordx2
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117 ; GFX9: v_pk_lshlrev_b16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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118 ; GFX9: v_pk_lshlrev_b16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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119 ; GCN: {{buffer|flat|global}}_store_dwordx2
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120 define amdgpu_kernel void @v_shl_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> addrspace(1)* %in) #0 {
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121 %tid = call i32 @llvm.amdgcn.workitem.id.x()
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122 %tid.ext = sext i32 %tid to i64
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123 %in.gep = getelementptr inbounds <4 x i16>, <4 x i16> addrspace(1)* %in, i64 %tid.ext
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124 %out.gep = getelementptr inbounds <4 x i16>, <4 x i16> addrspace(1)* %out, i64 %tid.ext
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125 %b_ptr = getelementptr <4 x i16>, <4 x i16> addrspace(1)* %in.gep, i32 1
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126 %a = load <4 x i16>, <4 x i16> addrspace(1)* %in.gep
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127 %b = load <4 x i16>, <4 x i16> addrspace(1)* %b_ptr
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128 %result = shl <4 x i16> %a, %b
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129 store <4 x i16> %result, <4 x i16> addrspace(1)* %out.gep
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130 ret void
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131 }
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132
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133 ; GCN-LABEL: {{^}}shl_v_imm_v4i16:
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134 ; GCN: {{buffer|flat|global}}_load_dwordx2
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135 ; GFX9: v_pk_lshlrev_b16 v{{[0-9]+}}, 8, v{{[0-9]+}}
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136 ; GFX9: v_pk_lshlrev_b16 v{{[0-9]+}}, 8, v{{[0-9]+}}
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137 ; GCN: {{buffer|flat|global}}_store_dwordx2
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138 define amdgpu_kernel void @shl_v_imm_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> addrspace(1)* %in) #0 {
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139 %tid = call i32 @llvm.amdgcn.workitem.id.x()
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140 %tid.ext = sext i32 %tid to i64
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141 %in.gep = getelementptr inbounds <4 x i16>, <4 x i16> addrspace(1)* %in, i64 %tid.ext
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142 %out.gep = getelementptr inbounds <4 x i16>, <4 x i16> addrspace(1)* %out, i64 %tid.ext
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143 %vgpr = load <4 x i16>, <4 x i16> addrspace(1)* %in.gep
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144 %result = shl <4 x i16> %vgpr, <i16 8, i16 8, i16 8, i16 8>
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145 store <4 x i16> %result, <4 x i16> addrspace(1)* %out.gep
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146 ret void
803732b1fca8 LLVM 5.0
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147 }
803732b1fca8 LLVM 5.0
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148
803732b1fca8 LLVM 5.0
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149 declare i32 @llvm.amdgcn.workitem.id.x() #1
803732b1fca8 LLVM 5.0
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150
803732b1fca8 LLVM 5.0
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151 attributes #0 = { nounwind }
803732b1fca8 LLVM 5.0
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152 attributes #1 = { nounwind readnone }